A State Element “Zoo”Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 43Slide 44Slide 45Slide 46Slide 47CAD for Sequential CircuitsSlide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70A State Element “Zoo”Edge-Triggered D Flip-FlopMaster-slave design is expensive in transistor countSame result can be had using a different design that uses only 6 NANDs  6 * 4 = 24 transistorsWant to design a circuit that responds on the positive edge of the clock pulse onlyPositive Edge-Triggered D Flip-FlopD Clock P4P3P1P25 6 1 2 3 Q Q 4Analysis of Previous Flip-FlopWhen Clock = 0P1 = P2 = 1  Q and Q' remain unchangedP4 = D' and P3 = DWhen Clock transitions 0  1P4 transmits thru gate 3  P2 = DP3 transmits thru gate 2  P1 = D'Q = D and Q' = D'After the 0  1 transition of ClockClock = 1  P1 = D', P2 = D, P3 = D, P4 = D' (memory)Clock transitions 1  0, back to P1 = P2 = 1 case (memory)If D = 0 at edge of Clock  P4 = 1 regardless of any further D changesIf D = 1 at edge of Clock  P2 = P3 = 1 regardless of any further D changesClear and Preset Controls on MS FFActive low clear and preset – asynchronous operation on a Master-Slave D Flip-FlopPreset = 0  Q = 1Clear = 0  Q = 0Q Q D Clock PresetClear D Q Q Clear PresetClear and Preset AgainSame operation, but using an edge-triggered D FFD Clock Q Q Clear PresetPresetClear D Q QSynchronous Clear ControlClear can also be done synchronously with the clockDClockQQClearDQQTerms ReviewedLatchTwo NANDs (or NORs) used to store one bitGated latchLatch with an control enable, called ClkTwo basic types: SR and D, both level sensitive Master-slave flip-flopState changes only on clock edge; made from two gated D latchesEdge-triggered flip-flopSame as MS FF with fewer transistorsT Flip-FlopToggle flip-flopOutput toggles on clock edgeD = T'Q + TQ'D Q Q Q Q T Clock T Q(t+1)0 Q(t)1 Q(t)'T Q QJK Flip-FlopJK behaves just like SR butremoves the S=R=1 problemOutput toggles on clock edgewhen J = K = 1D = JQ' + K'QJ K Q(t+1)0 0 Q(t)0 1 01 0 11 1 Q(t)'DQQQQJClockKJ QQKState Diagrams: DThe D flip-flop has the following state tableNote that changes on clock edge are always assumedThe corresponding state diagram isAgain, transitions occurs only on a clock edgeD Q(t+1)0 01 10 11001Q(t+1) = D D Q0 10 0 11 0 1characteristic equationState Diagrams: TThe T flip-flop state tableThe state diagram is0 10101Q(t+1) = TQ(t)' + T'Q(t) = T  Q(t)T Q(t+1)0 Q(t)1 Q(t)' T Q0 10 0 11 1 0characteristic equationState Diagrams: SRThe SR flip-flop state tableThe state diagram is0 1x0010x10Q(t+1) = S + R'Q(t)S R Q(t+1)0 0 Q(t)0 1 01 0 11 1 x S R Q00 01 11 100 0 0 x 11 1 0 x 1characteristic equationState Diagrams: JKThe JK flip-flop state tableThe state diagram is0 1x0x10x1xQ(t+1) = J Q(t)' + K' Q(t), orQ(t+1) = J Q(t)' + K' Q(t) + J K'J K Q(t+1)0 0 Q(t)0 1 01 0 11 1 Q(t)' J K Q00 01 11 100 0 0 1 11 1 0 0 1static hazard!!characteristic equationCharacteristic EquationsSummary of the characteristic equationsHow is the next state determined from the inputs and current state?Flip-flop Characteristic EquationD Q(t+1) = DTQ(t+1) = T  Q(t)SR Q(t+1) = S + R' Q(t)JK Q(t+1) = J Q(t)' + K' Q(t)Excitation TablesSummary of the excitation tablesFor each state transition Q(t)  Q(t+1), what input combination(s) will produce that transition?Q(t) Q(t+1) D T SR JK0 0 0 0 0x 0x0 1 1 1 10 1x1 0 0 1 01 x11 1 1 0 x0 x0Common TTL Flip-Flops7474 is a positive edge triggered D flip-flopActive low Preset (PRN) and Clear (CLRN)7473a is a negative edge triggered JK flop-flop7473 is the master-slave versionpositive edge triggeredRegistersA flip-flop stores one bit of informationWhen you want to store n bits  registern flip-flops usedClock is shared by all so action is synchronous with clock edgeSome common register typesSimple registerShift registerParallel access shift registerLots of counters: up counter, down counter, BCD counter, ring counter, Johnson counterSimple 4 Bit RegisterA standard 4 bit register using D flip flopsQ3Q2Q1Q0ClockParallel inputParallel outputDQQDQQDQQDQQ4 Bit Register with Load ControlControlling the load capabilityQ3Q2Q1Q0ClockParallel inputParallel outputDQQDQQDQQDQQLoadSimple Shift RegisterProvide only serial in/out accessD Q Q Clock D Q Q D Q Q D Q Q InOut Q 1 Q 2 Q 3 Q 4Action of Shift RegisterCan you use a level sensitive gated latch instead of a flip-flop?No!  The values would propagate during Clock = 1t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 Q 1 Q 2 Q 3 Q 4 Out = InParallel Access Shift RegisterProvide parallel data loadProvide parallel data readProvide serial shiftShift/Load = 0  Shift rightShift/Load = 1  LoadQ3Q2Q1Q0ClockParallel inputParallel outputShift/LoadSerialinputDQQDQQDQQDQQExample Problem: General ShifterDesign a parallel access (parallel data in / out) shift register that can load or shift either left or right – choice dictated by a control signalThen add the ability to "stay in memory"Don't forget to connect serial in to both MSB and LSBS1S0Function0 0 memory0 1 SHR1 0 SHL1 1 loadSolution: General ShifterQ3ClockParallel inputParallel outputDQQ0 1 2 3s1s0Q3DQQ0 1 2 3s1s0Q3DQQ0 1 2 3s1s0Q3DQQ0 1 2 3s1s0SRSI SLSI74164 Shifter8 bit serial in / parallel out shifter (used in modems)Active low clear (CLRN)Data-in provided by AND(A,B)Positive edge triggered shift right register74165 Shifter8 bit parallel in / serial out shifter (also used in modems)Active low asynchronous parallel load – output is HCLKIH is an active high clock inhibit – memory statePositive edge-triggered shift right register: SER is serial in74194 Bi-Directional Shifter4 bit bi-directional shifter with parallel loadActive low