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COMPILED UNIT DELAY SIMULATION FOR CYCLIC CIRCUITS Peter M Maurer Department of Computer Science and Engineering University of South Florida Tampa FL 33620 COMPILED UNIT DELAY SIMULATION FOR CYCLIC CIRCUITS ABSTRACT Three techniques are presented for handling cyclic circuits in a compiled unit delay simulation These techniques are based on the PC set Method and the Parallel Technique of compiled unit delay simulation The first technique called the Synchronous Parallel Technique is applicable only to synchronous circuits but provides significant performance improvements over interpreted unit delay simulation The second and third techniques called the Convergence Algorithm and the Asynchronous Parallel Technique are applicable to all circuits both synchronous and asynchronous The Convergence Algorithm which is based on the PC set Method provides significant performance increases for some circuits but performs poorly on others The Asynchronous Parallel Technique performs rather poorly and is covered only briefly COMPILED UNIT DELAY SIMULATION FOR CYCLIC CIRCUITS 1 Introduction Recent research in compiled simulation has provided a wide variety of techniques that can be used at different levels of the design hierarchy 1 9 Traditionally compiled simulation has focused on the zero delay model 5 7 but there are also several techniques that are based on the unit delay model 1 4 Existing simulation techniques fall into two broad categories which can be termed dynamic and oblivious With dynamic techniques the number of gates simulated varies from input vector to input vector based on both the content of the vectors and the values obtained from simulating various gates while with oblivious techniques the number of gates simulated per vector is constant By far the most common dynamic technique is event driven simulation Compiled unit delay simulation has been implemented using both dynamic techniques 1 2 and oblivious techniques 3 4 Two oblivious techniques are the PC set



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