Digital Design State Machines Timing Behavior Credits Slides adapted from J F Wakerly Digital Design 4 e Prentice Hall 2006 C H Roth Fundamentals of Logic Design 5 e Thomson 2004 R H Katz G Borriello Contemporary Logic Design 2 e Prentice Hall 2005 1 Timing in clocked sequential circuits The purpose of the clock signal is to synchronize the operation of flip flops and combinational logic in order to prevent timing problems In sequential logic we must examine not only the propagation delays through gates and wires but also the changes relative to clocking events of flip flops 2 Setup Hold Time Tsu Th input clock An input to a flip flop can be validly recognized only if it is stable before the clocking event for a minimum time interval Tsetup and it is stable after the clocking even for a minimum time interval Thold 3 Setup Hold Time cont d It is dangerous to allow input signals to change very close to the sampling event If setup or hold time constraints are not satisfied the input maybe interpreted as a 1 or a 0 or some unrecognizable value between 0 and 1 metastable value 4 Timing constraints in clocked sequential circuits din D clock C FF1 A Q combinational logic B FF2 D Q dout C Let s assume that din is applied in a way that satisfies setup and hold for FF1 and let s examine what will happen at FF2 5 Timing constraints in clocked sequential circuits cont d FF1 din D clock C Q Tclock tP A tFF1 combinational logic B FF2 D Q dout C Tsu2 Th2 clock din A B tFF1 Setup constraint tP tFF1 tP Tclock T tFF1 tP tFF1 tP T 6 Hold constraint Max Min delays FF1 Setup constraint din D clock C Q tP A tFF1 combinational logic tFF1 tP Tclock Tsu2 B FF2 D Q dout C tFF1 tP Th2 Hold constraint Unfortunately delays through gates are not constant Delays change with Supply Voltage Temperature and Manufacturing Process Setup constraint is more difficult to satisfy when delays are max V T P Hold constraint is more difficult to satisfy when delays are min V T P i v dvfor i constant i C if dv decreases dt must increases dt 7 Minimum Clock period for a Sequential circuit 8 Clock skew In this example if clock0 clock1 no skew setup at FF2 is violated tP FF1 din D clock C Q tFF1 skew clock0 tskew combinational logic tskew clock0 clock clock1 T 0 h din T 0 su B tFF1 tP Tsu2 Th2 B FF2 D Q dout C clock1 Positive skew makes easier to satisfy setup constraint tFF1 tP Tclock Tsu2 tskew Positive skew makes more difficult to satisfy hold constraint tFF1 tP Th2 tskew 9 Asynchronous Inputs Synchronous circuits can have asynchronous inputs Even a supposedly synchronous circuit like the D flip flop can have asynchronous inputs such as preset and clear In this case glitches makes asynchronous inputs extremely dangerous and should be avoided Sometimes asynchronous inputs come from signals that must pass from the outside world into the synchronous system In this case it is metastability to become an issue 10 Handling asynchronous inputs The best way to deal with asynchronous signals is to synchronize them to the clocked system 11 Handling asynchronous inputs cont d It is essential for asynchronous inputs to be synchronized at only one place in a system and as soon as possible Never allow asynchronous inputs to fan out to more than one flip flop Synchronize as soon as possible and then treat as synchronous signal Clocked Synchronous System Async Input D Q Synchronizer Q0 Async Input D Q D Q Clock Clock D Q Q1 Clock Q0 D Q Q1 Clock 12 Handling asynchronous inputs cont d Possible problem occurring when synchronizing at more than one place 13 Handling asynchronous inputs cont d Possible problem with procrastinating synchronization Example of combinational logic hiding the fact that there are two synchronizers Since different paths through combinational logic will have different delays the likelihood of an inconsistent result is even greater 14 Synchronization Failure What if the asynchronous input to the synchronizer FF changes too close to clock edge the FF may enter a metastable state neither a logic 0 nor 1 it may stay in this state an indefinite amount of time this is not likely in practice but has some probability logic 0 logic 1 Synchronization failure is said to occur if a system uses a synchronizer output while the output is still in metastable state The only way to recover from synchronization failure is to reset the entire circuit While the probability of synchronizer failure can be made small it can never be eliminated as long as there are asynchronous inputs 15 Synchronization Failure cont d logic 1 logic 0 logic 1 small but non zero probability that the FF output will get stuck in an in between state logic 0 FF In D C Q oscilloscope traces demonstrating synchronizer failure and eventual decay to steady state There are two ways to get a flip flop out the metastable state force the flip flop into a valid logic state using input signals that meet the specifications for minimum pulse width setup and hold time wait long enough so the flip flop comes out of metastability on its own 16 Metastability Resolution Time tr Maximum time that the output can remain metastable without causing synchronizer and system failure t r Tclk tcomb t su 17 Reducing the chance of Synchronizer Failure t r Tclk tcomb t su One way to reduce the probability of synchronizer failure is to use faster flip flops and lengthen the system s clock period This gives the synchronizer flip flop more time to enter a stable state A second strategy is to place two synchronizers in series Both flipflop must be metastable before the synchronization fails an event with low probability 18 Analysis of Metastable Timing 19 Analysis of Metastable Timing cont d tr e MTBF T0 f Mean Time Between synchronizer Failures tr resolution time f frequency of the flip flop clock number of asynchronous input changes per second applied to the flip flop T0 and constants that depends on the 20 electric characteristics of the flip flop Better synchronizers A way to improve the MTBF lengthen the clock applied to the synchronizer circuit n tclk 21 Better synchronizers cont d 22 Better synchronizers cont d At very high frequency the feasibility of the multicycle synchronizers is limited by the clock skew 23