Power-Aware CompilationWhy Worry about Power Dissipation?Power Dissipation TrendsCooking-Aware ComputingIntel vs. DuracellEnvironmentWhere Does the Juice Go in Laptops?Now We Know Why Power is ImportantPower: The BasicsPower Issues in MicroprocessorsCapacitive Power DissipationLowering Dynamic PowerPower vs. EnergySlide 14Power vs. Energy MetricsLow-Power Software StrategiesCode Optimizations for Low PowerSlide 18Slide 19ARM vs. THUMBMinimizing Memory Access CostsSlide 22Observation: Execution-time VariationObservation: Applications Tolerant to Deadline MissesExploiting Execution-time Variation and Tolerance to DeadlinesCompiler-Controlled DVFSSensor Network CompilationSlide 28Power-Aware CompilationCS 671April 22, 20082CS 671 – Spring 2008Why Worry about Power Dissipation?EnvironmentThermal issues: affect cooling, packaging, reliability, timingBatterylife3CS 671 – Spring 2008Power Dissipation TrendsHot PlateNuclear Reactor386486PentiumPentium ProPentium 2Pentium 3Pentium 4 (Prescott)Pentium 44CS 671 – Spring 2008Cooking-Aware Computing5CS 671 – Spring 2008Intel vs. DuracellNo Moore’s Law in batteries: 2-3%/year growth Processor (MIPS)Hard Disk (capacity)Memory (capacity)Battery (energy stored)0 1 2 3 4 5 616x14x12x10x8x 6x4x2x1xImprovement(compared to year 0)Time (years)6CS 671 – Spring 2008•Environment Protection Agency (EPA): computers consume 10% of commercial electricity consumption•Includes peripherals, possibly also manufacturing•Data center growth was cited as a contribution to the 2000/2001 California Energy Crisis•Equivalent power (with only 30% efficiency) for AC•CFCs used for refrigeration•Lap burn•Fan noiseEnvironment7CS 671 – Spring 2008Where Does the Juice Go in Laptops?8CS 671 – Spring 2008What can we do about it?Two components to the problem:•#1: Understand where and why power is dissipated•#2: Think about ways to reduce it at all levels of computing hierarchy•In the past, #1 is difficult to accomplish except at the circuit level•Consequently most low-power efforts were all circuit relatedNow We Know Why Power is Important9CS 671 – Spring 2008Power: The BasicsDynamic “switching” power vs. Static “leakage” power•Dynamic power dominates, but static power increasing in importance•Trends in eachStatic power: steady, per-cycle energy costDynamic power: capacitive and short-circuit•Capacitive power: charging/discharging at transitions from 01 and 10•Short-circuit power: power due to brief short-circuit current during transitions.•Most research focuses on capacitive, but recent work on others10CS 671 – Spring 2008TemperatureCapacitive (Dynamic) PowerStatic (Leakage) PowerMinimum Voltage20 cyclesDi/Dt (Vdd/Gnd Bounce)Voltage (V) Current (A) VOUT CL ISub VIN IGate Vin VoutCLVddPower Issues in Microprocessors11CS 671 – Spring 2008Capacitive Power DissipationPower ~ ½ CV2AfCapacitance:Function of wire length, transistor sizeSupply Voltage:Has been dropping with successive fab generationsClock frequency:Increasing…Activity factor:How often, on average, do wires switch?12CS 671 – Spring 2008Lowering Dynamic PowerReducing Vdd has a quadratic effect•Has a negative (~linear) effect on performance howeverLowering CL•May improve performance as well•Keep transistors small (keeps intrinsic capacitance (gate and diffusion) small)Reduce switching activity•A function of signal transition stats and clock rate•Clock gating idle units•Impacted by logic and architecture decisions13CS 671 – Spring 2008Power vs. Energy14CS 671 – Spring 2008Power vs. EnergyPower consumption in watts•Determines battery life in hours•Sets packaging limitsEnergy efficiency in joules•Rate at which energy is consumed over time•Energy = power * delay (joules = watts * seconds)•Lower energy number means less power to perform a computation at same frequency15CS 671 – Spring 2008Power vs. Energy MetricsPower-delay Product (PDP) = Pavg * t•PDP is the average energy consumed per switching eventEnergy-delay Product (EDP) = PDP * t•Takes into account that one can trade increased delay for lower energy/operation16CS 671 – Spring 2008Low-Power Software StrategiesCode running on CPU•Code optimizations for low powerCode accessing memory objects•SW optimizations for memoryData flowing on the buses•I/O coding for low powerCompiler controlled power managementCPUCacheMemory17CS 671 – Spring 2008Code Optimizations for Low PowerHigh-level operations (e.g. C statement) can be compiled into different instruction sequences–different instructions & ordering have different powerInstruction Selection•Select a minimum-power instruction mix for executing a piece of high level codeInstruction Packing & Dual Memory Loads• Two on-chip memory banks–Dual load vs. two single loads–Almost 50% energy savings18CS 671 – Spring 2008Code Optimizations for Low PowerReorder instructions to reduce switching effect at functional units and I/O buses•Cold scheduling minimizes instruction bus transitionsOperand swapping•Swap the operands at the input of multiplier•Result is unaltered, but power changes significantly!Other standard compiler optimizations•Intermediate level: Software pipelining, dead code elimination, redundancy elimination•Low level: Register allocation and other machine specific optimizations19CS 671 – Spring 2008Code Optimizations for Low PowerUse processor-specific instruction styles•on ARM the default int type is ~ 20% more efficient than char or short as the latter result in sign or zero extension•on ARM conditional instructions can be used instead of branches20CS 671 – Spring 2008ARM vs. THUMBARM – 32-bit, requires fewer instructionsTHUMB – 16-bit, more instructionsSwitching between ARM/THUMB takes time21CS 671 – Spring 2008Minimizing Memory Access CostsReduce memory access, better use of registers•Register access consumes less power than memory accessEasy way: minimize number of r/w operationsCache optimizations•Reorder memory accesses to improve cache hit ratesCan use existing techniques for high-performance code generation22CS 671 – Spring 2008Minimizing Memory Access CostsLoop optimizations such as loop unrolling, loop fusion also reduce memory power consumptionMore effective: explicitly target minimization of switching activity on I/O busses and exploiting memory hierarchy•Data allocation to