Harvard ArchitecturePIC18F Microcontroller FamiliesMicrocontroller with the Harvard ArchitecturePIC18F452/4520 Memory - ExamplePIC18F – MCU and MemoryPIC18F – MCU and Memory – Design ProblemPIC18F – MCU and Memory – Design ProblemMicroprocessor Unit (1 of 3)Microprocessor Unit (2 of 3)Microprocessor Unit (3 of 3)PIC18F - Address BusesData Bus and Control SignalsExamplesInstructionsSlide 16Slide 17PIC18F452/4520 MemoryPIC18F452/4520 – Data Memory with Access BanksData Memory OrganizationPIC18F452 I/O PortsProcesses and Conditions of Data TransferSlide 23Slide 24MCU Support Devices (1 of 2)PIC18F Special FeaturesPIC18F4X2 Architecture Block DiagramPIC16F87 Architecture Block DiagramSlide 29Questions - Table 2-9 (pp. 46 and 48)PIC18F Instructions and Assembly LanguageInstruction Description and IllustrationsInstruction Set OverviewIllustration: Displaying a Byte at an I/O Port (1 of 5)Illustration (2 of 5)Illustration (3 of 5)PIC18 SimulatorSlide 38Questions - PIC18 Simulator IDEExampleIllustration (4 of 5)Microcontroller Architecture—PIC18F FamilyChapter 2Harvard ArchitectureVon Neumann Architecture:Fetches instructions and data from a single memory spaceLimits operating bandwidthHarvard Architecture:Uses two separate memory spaces for program instructions and dataImproved operating bandwidthAllows for different bus widthsPIC18F Microcontroller FamiliesPIC microcontrollers are designed using the Harvard Architecture which includes:Microprocessor unit (MPU)Program memory for instructionsData memory for dataI/O portsSupport devices such as timersMicrocontroller with the Harvard ArchitecturePIC18F452/4520 Memory - ExampleProgram Memory: 32 K (215)Address range: 000000 to 007FFFH16-bit registersData Memory: 4 KAddress range: 000 to FFFH8-bit registersData EEPROMNot part of the data memory spaceAddressed through special function registers http://www.microchip.com/ParamChartSearch/chart.aspx?branchID=1004&mid=10&lang=en&pageId=74PIC18F – MCU and Memory2 MB2214 KB21216 bit8 bitPIC18F – MCU and Memory – Design ProblemDesign a micro controller with the following specifications Specify bus widths. Program Memory: 32 KData Memory: 4 KIn your design show where the counter registers are located In your design show where the working registers are located (which part of the microprocessor unit) Show where the read/write lines are connected to – specify the direction of each. 32 K (215)PIC18F – MCU and Memory – Design Problem Design a micro controller with the following specifications Specify bus widths. Program Memory: 32 K (215)Address range: 000000 to 007FFFH16-bit registersData Memory: 4 KAddress range: 000 to FFFH8-bit registers32 K (215)Microprocessor Unit (1 of 3)Includes Arithmetic Logic Unit (ALU), Registers, and Control UnitArithmetic Logic Unit (ALU)WREG – working registerStatus register that stores flagsInstruction decoder – when the instruction is fetched it goes into the IDMicroprocessor Unit (2 of 3)RegistersBank Select Register (BSR)4-bit register used in direct addressing the data memory File Select Registers (FSRs)16-bit registers used as memory pointers in indirect addressing data memory Program Counter (PC)21-bit register that holds the program memory address while executing programsMicroprocessor Unit (3 of 3)Control unit Provides timing and control signals to various Read and Write operationsPIC18F - Address BusesAddress bus21-bit address bus for program memory addressing capacity: 2 MB of memory12-bit address bus for data memory addressing capacity: 4 KB of memoryData Bus and Control SignalsData bus16-bit instruction/data bus for program memory8-bit data bus for data memoryControl signalsRead and WriteExamplesRefer to your notes!00000000Instructions8-bit Program Memory16-bit Program Memory1100000000111100kkkkkkkkkkkkkkkk11111100kkkkkkkkkkkkkkkk8-bit Instruction on typical 8-bit MCUExample: Freescale ‘Load Accumulator A’:• 2 Program Memory Locations• 2 Instruction Cycles to Execute16-bit Instruction on PIC18 8-bit MCUExample: ‘Move Literal to Working Register’• 1 Program Memory Location• 1 Instruction Cycle to ExecuteLimits BandwidthIncreases Memory Size RequirementsSeparate busses allow different widths2k x 16 is roughly equivalent to 4k x 8inst kmovlw kFlash (4K)EEPROM – can be accessed individually36 I/O ports F FLASH C EPROMPIC18F452/4520 MemoryProgram memory with addresses (Flash)Data memory with addressesAlso called Data Register or File Register FFF=212=16x256=4096=4KPIC18F452/4520 – Data Memory with Access BanksThree ways to access data registers:Direct using Bank Select Registers (BSR)Bank address (4-bit) + Instruction (8-bit)Indirect using File Select Registers (FSR)FSR contains the address of the data registerHence, MPU uses FSRAccess Bank using General Purpose Registers (GPR)Data Memory OrganizationData Memory up to 4k bytesData register map - with 12-bit address bus 000-FFFDivided into 256-byte banksThere are total of F banksHalf of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selectedFFF=212=16x256=4096=4KAccess RAMAccess RAMPIC16F8F2520/4520Register File (data memory) Map000h07Fh256 BytesBank 0 GPRBank 0 GPRBank 1GPRBank 1GPRBank 2GPRBank 2GPRBank 13GPRBank 13GPRBank 14GPRBank 14GPRBank 15 GPRBank 15 GPRAccess SFRAccess SFRAccess RAM (GPR)Access RAM (GPR)Access SFRAccess SFR080h0FFh100h1FFh200h2FFhD00hDFFhE00hEFFhF00hFFFhF7FhF80h00h7Fh80hFFhAccess BankGPR=General Purpose Reg. SFR=Special Function Reg.PIC18F452 I/O PortsFive I/O portsPORT A through PORT EMost I/O pins are multiplexedGenerally have eight I/O pins with a few exceptionsAddresses already assigned to these ports in the design stageEach port is identified by its assigned Special Function Registers (SFR) – look at the previous slidePORTA (address of F80)PORTB (address of F81) these are part of data memory or register fileTRISB must be set to specify signal direction of PORT B.Processes and Conditions of Data TransferInterrupt is a process of communication between two devices If provides efficient communication between the two devices Examples: Sending a file to a printer, pressing a key on the key board External or Internal to
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