FUNDAMENTAL DDS ARCHITECTUREALIASING IN DDS SYSTEMSDDS SYSTEMS AS ADC CLOCK DRIVERSAMPLITUDE MODULATION IN A DDS SYSTEMSPURIOUS FREE DYNAMIC RANGE CONSIDERATIONS IN DDS SYSTEMSREFERENCES:MT-085TUTORIAL Fundamentals of Direct Digital Synthesis (DDS) FUNDAMENTAL DDS ARCHITECTURE With the widespread use of digital techniques in instrumentation and communications systems, a digitally-controlled method of generating multiple frequencies from a reference frequency source has evolved called Direct Digital Synthesis (DDS). The basic architecture is shown in Figure 1. In this simplified model, a stable clock drives a programmable-read-only-memory (PROM) which stores one or more integral number of cycles of a sinewave (or other arbitrary waveform, for that matter). As the address counter steps through each memory location, the corresponding digital amplitude of the signal at each location drives a DAC which in turn generates the analog output signal. The spectral purity of the final analog output signal is determined primarily by the DAC. The phase noise is basically that of the reference clock. Because a DDS system is a sampled data system, all the issues involved in sampling must be considered: quantization noise, aliasing, filtering, etc. For instance, the higher order harmonics of the DAC output frequencies fold back into the Nyquist bandwidth, making them unfilterable, whereas, the higher order harmonics of the output of PLL-based synthesizers can be filtered. There are other considerations which will be discussed shortly. fcADDRESSCOUNTERSINLOOKUPTABLEN-BITSCLOCKREGISTERLPFDACfoutLOOKUP TABLE CONTAINS SINEDATA FOR INTEGRAL NUMBEROF CYCLESN-BITSfcADDRESSCOUNTERSINLOOKUPTABLEN-BITSCLOCKREGISTERLPFDACfoutLOOKUP TABLE CONTAINS SINEDATA FOR INTEGRAL NUMBEROF CYCLESN-BITS Figure 1 : Fundamental Direct Digital Synthesis System Rev.0, 10/08, WK Page 1 of 9MT-085 A fundamental problem with this simple DDS system is that the final output frequency can be changed only by changing the reference clock frequency or by reprogramming the PROM, making it rather inflexible. A practical DDS system implements this basic function in a much more flexible and efficient manner using digital hardware called a Numerically Controlled Oscillator (NCO). A block diagram of such a system is shown in Figure 2. fcSERIALOR BYTELOADREGISTERnnFREQUENCY CONTROLPHASEREGISTERLPFDACPARALLELDELTAPHASEREGISTERMCLOCKnnPHASE ACCUMULATORnPHASETRUNCATION12-19 BITSAMPLITUDETRUNCATION2n=foM • fcN-BITSn = 24 - 48 BITSPHASE-TOAMPLITUDECONVERTERM = TUNING WORDSYSTEM CLOCK(10-14) Figure 2: A Flexible DDS System The heart of the system is the phase accumulator whose contents is updated once each clock cycle. Each time the phase accumulator is updated, the digital number, M, stored in the delta phase register is added to the number in the phase accumulator register. Assume that the number in the delta phase register is 00...01 and that the initial contents of the phase accumulator is 00...00. The phase accumulator is updated by 00...01 on each clock cycle. If the accumulator is 32-bits wide, 232 clock cycles (over 4 billion) are required before the phase accumulator returns to 00...00, and the cycle repeats. The truncated output of the phase accumulator serves as the address to a sine (or cosine) lookup table. Each address in the lookup table corresponds to a phase point on the sinewave from 0° to 360°. The lookup table contains the corresponding digital amplitude information for one complete cycle of a sinewave. (Actually, only data for 90° is required because the quadrature data is contained in the two MSBs). The lookup table therefore maps the phase information from the phase accumulator into a digital amplitude word, which in turn drives the DAC. This is shown graphically using the "phase wheel" in Figure 3. Page 2 of 9MT-085Consider the case for n = 32, and M = 1. The phase accumulator steps through each of 232 possible outputs before it overflows and restarts. The corresponding output sinewave frequency is equal to the input clock frequency divided by 232. If M=2, then the phase accumulator register "rolls over" twice as fast, and the output frequency is doubled. This can be generalized as follows. n8121620242832482n=foM • fcNumber of Points = 2n2564,09665,5361,048,57616,777,216268,435,4564,294,967,296281,474,976,710,656M = JUMP SIZE Figure 3: Digital Phase Wheel For an n-bit phase accumulator (n generally ranges from 24 to 32 in most DDS systems), there are 2n possible phase points. The digital word in the delta phase register, M, represents the amount the phase accumulator is incremented each clock cycle. If fc is the clock frequency, then the frequency of the output sinewave is equal to: .2fMfnco⋅= Eq. 1 This equation is known as the DDS "tuning equation." Note that the frequency resolution of the system is equal to fc/2n. For n = 32, the resolution is greater than one part in four billion! In a practical DDS system, all the bits out of the phase accumulator are not passed on to the lookup table, but are truncated, leaving only the first 13 to 15 MSBs. This reduces the size of the lookup table and does not affect the frequency resolution. The phase truncation only adds a small but acceptable amount of phase noise to the final output. (See Figure 4). Page 3 of 9MT-085 NORMALIZED FREQUENCY - fOUT/fCLK0-20-40-60-80-100-1200 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Figure 4: Calculated Output Spectrum Shows 90 dB SFDR for 15-bit Phase Truncation The resolution of the DAC is typically 2 to 4 bits less than the width of the lookup table. Even a perfect N-bit DAC will add quantization noise to the output. Figure 4 shows the calculated output spectrum for a 32-bit phase accumulator, 15-bit phase truncation. The value of M was chosen so that the output frequency was slightly offset from 0.25 times the clock frequency. Note that the spurs caused by the phase truncation and the finite DAC resolution are all at least 90 dB below the fullscale output. This performance far exceeds that of any commercially available 12-bit DAC and is adequate for most applications. The basic DDS system described above is extremely flexible and has high resolution. The frequency can be changed instantaneously with no phase discontinuity by simply changing the contents of the M-register. However, practical DDS systems first require the