UConn ECE 3111 - An Introduction to Synopsys Design Automation (24 pages)

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An Introduction to Synopsys Design Automation



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An Introduction to Synopsys Design Automation

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Pages:
24
School:
University Of Connecticut
Course:
Ece 3111 - Systems Analysis
Systems Analysis Documents

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An Introduction to Synopsys Design Automation Jeremy Lee jslee engr uconn edu November 7 2007 Introduction Why the need CAD tools Time to market decreasing a year Designs are becoming more complex System on a chip Synopsys is one of many EDA vendors vying for designer mind share Introduction cont Why do we in academia need CAD tools Keep our research relevant to industry Know what needs improving academia on cutting edge What will be covered Overview of tools What s available What do the tools do Example Flow Will not be a step by step how to Getting Synopsys Started at UConn Synopsys Linux binaries are available on the ECS fileserver apps ecs apps software synopsys Releases Y 2006 Z 2007 bashrc and cshrc files located at apps ecs apps software synopsys etc Synopsys directory can be mounted directly using NFS files ApplicationDirectories nfs ecsapps software synopsys Tools are location dependent Must be in same directory structure as on server Gui or console modes Synopsys Galaxy Platform at UConn Y 2006 Design Automation Design Compiler JupiterXT Astro Physical Compiler Sign off Validation Verification PrimeTime SI PX VX PrimePower Star RCXT Formality VCS Nanosim HSpice Design for Test DFT Compiler DFT MAX TetraMAX Design Automation Design Compiler Physical Compiler Layout aware RTL to gate level synthesis JupiterXT RTL to gate level synthesis Floorplanning tool Astro Placement and routing Design Compiler DC Synthesizes gate level netlists from RTL level Optimizes netlists Removes unused or redundant logic Tie off nets that are constant Requires standard cell library timing characterization Attempts to meet timing and area constraints SDC File Libraries Supposed to be provided by fab Gates in standard cell library Operating condition corners Gate delays Wire load models Compensates delay for fan out SDC File Synopsys Design Constraints SDC Set up clock period Specifies timing and area requirements that are to be met during mapping and optimization SDC Constraints



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