An Introduction to Synopsys Design AutomationIntroductionIntroduction (cont.)What will be covered?Getting Synopsys Started at UConnSynopsys Galaxy Platform at UConn (Y-2006)Design AutomationDesign Compiler (DC)LibrariesSDC FileSDC ConstraintsDC FlowJupiterXTAstroAstro FlowSlide 16Sign-off/Validation/VerificationSign-off/Validation/Verification (cont.)PrimeTime SI/PX/VX (PT-SI/PX/VX)PT-SI/PX/VX FlowPutting the Pieces TogetherSlide 22Design for TestAdditional ReadingAn Introduction to Synopsys Design AutomationJeremy [email protected] 7, 2007IntroductionWhy the need CAD tools?Time to market decreasing (< a year)Designs are becoming more complex (System-on-a-chip)Synopsys is one of many EDA vendors vying for designer mind-shareIntroduction (cont.)Why do we (in academia) need CAD tools?Keep our research relevant to industryKnow what needs improving (academia on cutting edge)What will be covered?Overview of toolsWhat’s available?What do the tools do?Example FlowWill not be a step-by-step how-to.Getting Synopsys Started at UConnSynopsys Linux binaries are available on the ECS fileserver:/apps/ecs-apps/software/synopsysReleases: Y-2006, Z-2007bashrc and cshrc files located at/apps/ecs-apps/software/synopsys/etcSynopsys directory can be mounted directly using NFS files:/ApplicationDirectories/nfs/ecs-apps/software/synopsysTools are location dependentMust be in same directory structure as on serverGui or console modesSynopsys Galaxy Platform at UConn (Y-2006)Design CompilerJupiterXTAstroPhysical CompilerDesign AutomationPrimeTime SI/PX/VXPrimePowerStar-RCXTFormalityVCSNanosimHSpiceSign-off / Validation / VerificationDFT CompilerDFT MAXTetraMAXDesign for TestDesign AutomationDesign CompilerRTL to gate-level synthesisPhysical CompilerLayout-aware RTL to gate-level synthesisJupiterXTFloorplanning toolAstroPlacement and routingDesign Compiler (DC)Synthesizes gate level netlists from RTL-levelOptimizes netlistsRemoves unused or redundant logicTie-off nets that are constantRequires standard cell library timing characterizationAttempts to meet timing and area constraints (SDC File)LibrariesSupposed to be provided by fabGates in standard cell libraryOperating condition cornersGate delaysWire load modelsCompensates delay for fan-outSDC FileSynopsys Design Constraints (SDC)Set up clock periodSpecifies timing and area requirements that are to be met during mapping and optimizationSDC ConstraintsInput DelayOutput DelayDriving CellLoadDC FlowReadNetlistMap toLink Library(if gate-level)Apply ConstraintsNetlistWrite-outOptimizedNetlistSDCCons.Map toTarget Libraryand OptimizeReadLibrariesLibrariesJupiterXTFloorplanningPower/Ground Network PlanningPin/Power pad placementBlockagesMemory placementPerformed through GUI or command lineAstroPlacement and routing toolRequires physical information of standard cell library (provided by fab)Graphic Data System (GDSII)Library Exchange Format (LEF)Physical design in multiple formatsGSDIIDesign Exchange Format (DEF)Astro FlowImportNetlist andConstraintsNetlistOpenLibrariesLibrariesRead/SetupFloorplanRunPlacementRoutingPhysicalDesignSDCCons.Synopsys Galaxy Platform at UConn (Y-2006)Design CompilerJupiterXTAstroPhysical CompilerDesign AutomationPrimeTime SI/PX/VXPrimePowerStar-RCXTFormalityVCSNanosimHSpiceSign-off / Validation / VerificationDFT CompilerDFT MAXTetraMAXDesign for TestSign-off/Validation/VerificationFormalityVerify netlistPrimeTime SI/PX/VXTiming validation (signal-integrity, power-aware, variation-aware)PrimePowerPower validationSign-off/Validation/Verification (cont.)Star-RCXTExtraction toolVCSHDL simulatorNanoSimHDL simulator w/ parasiticsHSpiceSpice simulatorPrimeTime SI/PX/VX (PT-SI/PX/VX)Calculates and reports path delaysVerify operating frequency after logic synthesisCan be back-annotated with extracted parasitics for post-layout verificationPT-SI/PX/VX FlowReadNetlistMap toLink Library(if gate-level)Apply ConstraintsNetlistSDCCons.ReadLibrariesLibrariesBack-annotatedesignReportTiming resultsMeetspec?ECONextphaseYesNoParasiticsProcessVariation*New*Putting the Pieces TogetherRTLNetlistSDCCons.LogicSynthesisGateNetlistLogicLibrariesSign-offFailsPassesPhysicalSynthesisPhysicalLibrariesLayoutExtractionSign-offFailsPassesToFabSynopsys Galaxy Platform at UConn (Y-2006)Design CompilerJupiterXTAstroPhysical CompilerDesign AutomationPrimeTime SI/PX/VXPrimePowerStar-RCXTFormalityVCSNanosimHSpiceSign-off / Validation / VerificationDFT CompilerDFT MAXTetraMAXDesign for TestDesign for TestDFT CompilerScan chain insertionDFT MaxTest compression toolTetraMaxAutomatic test pattern generation (ATPG)Additional ReadingSynopsys Websitewww.synopsys.comDocumentationSynopsys OnLine Documenation (SOLD)Available on any of the UConn ECS Linux serversElectronic Synopsys Users Group