Computer Systems Lab 1– 1 – Basic Logic Gates Object To investigate the properties of the various types of logic gates, and construct some useful combinations of thesegates. Parts (1) 7400 Quad 2-input NAND gate(1) 7402 Quad 2-input NOR gate(1) 7404 Hex inverter(1) 7408 Quad 2-input AND gate(1) 7432 Quad 2-input OR gate(1) 7486 Quad 2-input XOR gate Study sections Computer Systems , Fourth Edition, Jones and Bartlett Publishers: Section 10.1, Boolean Algebra and Logic Gates;Section 10.2, Combinational Analysis. General information The integrated circuit (IC) gates in these labs are of the transistor–transistor logic (TTL) family. TTL logic used to bethe most common technology used in the manufacture of computer systems. Because of the lower power require-ments and higher density of complementary metal oxide semiconductor (CMOS) technology, however, some form ofit is common in today’s large scale integrated circuits. TTL gates require +5VDC for a voltage source (VCC) at pin 14for all ICs in this experiment and ground (GND) at pin 7. The pin numbering system for the ICs is shown in the partslist.Most integrated circuit chips contain multiple gates. Common configurations are: four gates of 2 inputs each, threegates of 3 inputs each, or two gates of 4 inputs each. Caution Different types of gates (NAND, NOR, etc.) may have their inputs and outputs connected to different pins. Pay closeattention during all experiments so that you connect the pins as they are numbered, or the IC may be destroyed. Therule is that you may connect one output to several inputs, but never connect two outputs together. Always turn thepower off when connecting or disconnecting wires. Procedure In the following procedure SW stands for switch and is used to set the input level. The switch inputs come from theComputer Systems Lab 1– 2 – switches on the panel of the breadboard kit. Also, L stands for light, which you implement by connecting an output toone of the light emitting diodes (LEDs) on the panel. As a rule you should make all connections as short as possibleexcept for the switch input leads and the light output leads. 1. OR gate function (A + B) Install a 7432 Quad 2-input OR gate on the breadboard and make the (VCC) and (GND) connections. Be sure poweris off. Make the connections to the gate as shown in Figure 1. The designation 1/4 7432 means that you are using oneof the four gates that are provided by the 7432 chip. The small numbers inside the gate are the pin numbers from thechip package. Turn on the power. Set the switches as indicated in the truth table of Figure 1 and record the light con-ditions (on = 1), (off = 0). 2. Two-level 3-input OR gate Make the connections as shown in Figure 2. Set the switches as shown in the truth table of Figure 2 and record thelight conditions.Figure 1SW1 SW2 LA0 00 11 01 1123SW1SW2LA1/4 7432Figure 2SW1 SW2 SW3 LA LB0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1123SW1SW2LA456SW3LB7432Computer Systems Lab 1– 3 – 3. Three-level 4-input OR gate Wire the circuit shown in Figure 3. Set switches as indicated in the truth table of Figure 3 and record the light condi-tions.Figure 3SW1 SW2 SW3 SW4 LA LB LC0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1123SW1SW2LA456SW37432LB9108LCSW4Computer Systems Lab 1– 4 – 4. AND gate function (AB) Turn off the power and remove the 7432 OR gate. Without changing the wiring replace with a 7408 Quad 2 inputAND gate. The schematic representation of the three level 2 input AND gate is shown in Figure 4. Set the switches asindicated in the truth table of Figure 4 and record the light conditions.Figure 4SW1 SW2 SW3 SW4 LA LB LC0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1SW1SW2LASW37408LBLCSW41234569108Computer Systems Lab 1– 5 – Propagation delay is the time between application of a change to the input and the appearance of the resulting changeon the output. While the time is insignificant in human terms (on the order of 10-15 nanoseconds for TTL technol-ogy), it often becomes critical in high speed circuits. The above circuit contains three propagation delays, hence thename three-level circuit. However, it may be reduced to a two level circuit using the same number of gates.Draw the equivalent two-level 4-input circuit using three 2-input AND gates in the space below. Only the output (LC)column of the truth table need be satisfied. You do not need to construct the circuit in the lab.Equivalent 2-level circuit: 5. NOR gate function (A + B) ! Install a 7402 Quad 2-input NOR gate as shown in Figure 5. Set the switches as indicated in the truth table of Figure5 and record the light indications. Note that the truth table is identical but reversed to that of the OR gate. Thus theNOR gate is identical to an OR gate followed by an inverter.Figure 5SW1 SW2 LA0 00 11 01 1SW1SW2LA1/4 7402231Computer Systems Lab 1– 6 – 6. NAND gate function (AB) ! Turn off the power and remove the 7402 NOR gate. Install a 7400 Quad 2-input NAND gate and connect as shown inFigure 6. Set the switches as indicated in the truth table of Figure 6 and record the light conditions. Note that theNAND function is to the AND as the NOR is to the OR. 7. The negated-input OR and the negated-input AND concept Connect the circuit shown in Figure 7. Set the switches as indicated in the truth table of Figure 7 and record the lightindications. Compare the truth table of Figure 7 with that of the 4-input AND gate of Figure 4. Note that the outputcolumns (LC) are identical. Therefore the circuit of Figure 7 is performing the 4-input AND function, although thesecond level gate is a NOR gate.Figure 6SW1 SW2 LA0 00 11 01 1SW1SW2LA1/4 7400123Computer Systems Lab 1– 7 – Inspection of the circuit in Figure 7 is misleading as to its actual function, due to the NOR symbol, especially if itwere part of a complex logic diagram which was being analyzed. Therefore, it has become conventional to draw thenegated input AND function of the NOR gate as in Figure 8.Figure 7SW1 SW2 SW3 SW4 LA LB LC0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1SW1SW2LASW37400LBLCSW42317402123456Computer Systems Lab 1– 8 – Figure 9 shows the equivalent circuit of Figure 7, redrawn so that its function becomes readily apparent. In your mindyou can simply cancel the effect of two inverters in a