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Soft Error Analysis



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Soft Error Analysis and Optimizations of C elements in Asynchronous Circuits Balaji Vaidyanathan Yuan Xie N Vijaykrishnan CSE Department The Pennsylvania State University University Park PA 16802 USA Email bvaidyan yuanxie vijay cse psu edu Hao Zheng CSE Department University of South Florida Tampa FL 33620 USA Email zheng cse usf edu and Muller C element and their soft error vulnerability is examined in Section 4 Section 5 provides various methods to enhance the soft error tolerance of Muller C element Finally we summarize our work in section 6 Abstract Control circuit in an asynchronous design is comprised mostly of Muller C elements Previous work has concentrated on power performance and area issues of various CMOS implementations of the C element In this paper we carried out a thorough soft error analysis of four popular CMOS implementations of the Muller C element It shows that SIL implementation has the best soft error resilience Optimization techniques to improve the soft error resilience of C elements are proposed Results show 2x improvements in critical charge by using our techniques Finally analysis of power performance and area tradeoff is carried out for the optimized C element II R ELATED W ORK Work in 7 8 has dealt with the unidirectional and asymmetric errors occurring in the asynchronous buses They use Error Detection and Correction EDC codes to detect transmission completion error occurrences and correct them 6 shows the VLSI implementation of asynchronous decoder for unordered codes for DI communication A more robust EDC codes for DI and Semi Delay Insensitive SDI circuits is provided in 9 The work presented in 5 deals with converting circuit errors and invalid tokens to deadlock and also presents layout techniques to mitigate delay faults in QDI circuits In 4 transient fault sensitivity of the QDI circuits is analyzed using logic level fault models and circuit duplication is proposed to eliminate single transient faults In 5 the authors have used



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