Dr. Michael Perrone, IBM. 1 6.189 IAP 2007 MIT6.189 IAP 2007Lecture 2Introduction to the Cell ProcessorMichael Perrone ([email protected])2 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Class Agenda● Motivation for multicore chip design● Cell basic design concept● Cell hardware overview Cell highlights  Cell processor Cell processor components● Cell performance characteristics● Cell application affinity● Cell software overview Cell software environment Development tools Cell system simulator Optimized libraries● Cell software development considerations ● Cell bladeDr. Michael Perrone, IBM. 3 6.189 IAP 2007 MIT6.189 IAP 2007Lecture 2Where have all the gigahertz gone?4 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Technology Scaling – We’ve hit the wall1988 1992 1996 2000 2004 2008 20120.20.40.60.8124681020 Conventional Bulk CMOS SOI (silicon-on-insulator) High mobility Double-GateRelative Device PerformanceYear?5 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Power Density – The fundamental problem11010010001.5μ1μ0.7μ0.5μ0.35μ0.25μ0.18μ0.13μ0.1μ0.07μi386i486Pentium®Pentium Pro®Pentium II®Pentium III®W/cm2Hot PlateNuclear ReactorSource: Fred Pollack, Intel. New Microprocessor Challenges in the Coming Generations of CMOS Technologies, Micro326 6.189 IAP 2007 MITDr. Michael Perrone, IBM.0.010.110.0010.010.11101001000Gate Length (microns)Active PowerPassive Power1994 2004What’s Causing The Problem?10S Tox=11AGate dielectric approachinga fundamental limit(a few atomic layers)Power Density (W/cm2)65 nMGate Stack7 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Steam Iron5W/cm2Has This Ever Happened Before?8 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Steam Iron5W/cm2?Has This Ever Happened Before?opportunityDr. Michael Perrone, IBM. 9 6.189 IAP 2007 MIT6.189 IAP 2007Lecture 2The Multicore Approach10 6.189 IAP 2007 MITDr. Michael Perrone, IBM.CellSystems and Technology Group11 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Cell History● IBM, SCEI/Sony, Toshiba Alliance formed in 2000● Design Center opened in March 2001 Based in Austin, Texas● Single Cell BE operational Spring 2004● 2-way SMP operational Summer 2004● February 7, 2005: First technical disclosures● October 6, 2005: Mercury Announces Cell Blade ● November 9, 2005: Open Source SDK & Simulator Published● November 14, 2005: Mercury Announces Turismo Cell Offering● February 8, 2006 IBM Announced Cell Blade Systems and Technology GroupDr. Michael Perrone, IBM. 12 6.189 IAP 2007 MIT6.189 IAP 2007Lecture 2Cell Basic Design Concept13 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Cell Basic Concept● Compatibility with 64b Power Architecture™ Builds on and leverages IBM investment and community● Increased efficiency and performance Attacks on the “Power Wall”– Non Homogenous Coherent Multiprocessor– High design frequency @ a low operating voltage with advanced power management Attacks on the “Memory Wall”– Streaming DMA architecture– 3-level Memory Model: Main Storage, Local Storage, Register Files Attacks on the “Frequency Wall”– Highly optimized implementation– Large shared register files and software controlled branching to allow deeper pipelines● Interface between user and networked world Image rich information, virtual reality Flexibility and security● Multi-OS support, including RTOS / non-RTOS Combine real-time and non-real time worlds14 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Cell Design Goals● Cell is an accelerator extension to Power Built on a Power ecosystem Used best know system practices for processor design● Sets a new performance standard  Exploits parallelism while achieving high frequency Supercomputer attributes with extreme floating point capabilities Sustains high memory bandwidth with smart DMA controllers● Designed for natural human interaction Photo-realistic effects Predictable real-time response Virtualized resources for concurrent activities● Designed for flexibility Wide variety of application domains Highly abstracted to highly exploitable programming models Reconfigurable I/O interfaces Virtual trusted computing environment for security15 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Cell Synergy● Cell is not a collection of different processors, but a synergistic whole Operation paradigms, data formats and semantics consistent  Share address translation and memory protection model ● PPE for operating systems and program control● SPE optimized for efficient data processing SPEs share Cell system functions provided by Power Architecture MFC implements interface to memory– Copy in/copy out to local storage● PowerPC provides system functions Virtualization Address translation and protection External exception handling● EIB integrates system as data transport hubDr. Michael Perrone, IBM. 16 6.189 IAP 2007 MIT6.189 IAP 2007Lecture 2Cell Hardware Components17 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Cell Chip18 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Cell Features● Heterogeneous multicore system architecture Power Processor Element for control tasks Synergistic Processor Elements for data-intensive processing● Synergistic Processor Element (SPE) consists of  Synergistic Processor Unit (SPU) Synergistic Memory Flow Control (MFC)– Data movement and synchronization– Interface to high-performance Element Interconnect Bus16B/cycle (2x)16B/cycleBICFlexIOTMMICDual XDRTM16B/cycleEIB (up to 96B/cycle)16B/cycle64-bit Power Architecture with VMX PPESPELSSXUSPUMFCPXUL1PPU16B/cycleL232B/cycleLSSXUSPUMFCLSSXUSPUMFCLSSXUSPUMFCLSSXUSPUMFCLSSXUSPUMFCLSSXUSPUMFCLSSXUSPUMFC19 6.189 IAP 2007 MITDr. Michael Perrone, IBM.Cell Processor Components (1)● Power Processor Element (PPE):  General purpose, 64-bit RISCprocessor (PowerPC AS 2.0.2) 2-Way hardware multithreaded L1 : 32KB I ; 32KB D L2 : 512KB Coherent load / store VMX-32 Realtime Controls– Locking L2 Cache & TLB– Software / hardware managed TLB– Bandwidth / Resource Reservation– Mediated Interrupts● Element Interconnect Bus (EIB): Four 16 byte data rings supporting multiple simultaneous transfers per ring 96Bytes/cycle peak bandwidth  Over 100 outstanding requestsIn the Beginning– the solitary Power ProcessorCustom Designed– for high frequency, space, and power efficiency96 Byte/CycleElement Interconnect BusPower