QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigmusing Process NetworksSunil Shukla1, 2, Neil W. Bergmann1,J¨urgen Becker21University of Queensland2Universit¨at KarlsruheInformation Technology & Electrical Engg. Institut f¨ur Technik der Informationsverarbeitung (ITIV)St. Lucia, QLD 4072, Australia 76131 Karlsruhe, Germany{sunil, n.bergmann}@itee.uq.edu.au [email protected] applications can be suitably represented using Pro-cess Network Models. This paper uses a modification ofKahn Process Network to solve the problem of finding anoptimum architectural template for coarse grain array onper application basis. By applying the model at architec-tural level in QUKU, better hardware efficiency is achievedfor a wide domain of applications. A few widely used DSPalgorithms have been presented to demonstrate the applica-tion of process network models into architectural templategeneration in QUKU.1. IntroductionFPGAs have come a long way from just being used asa platform for implementing glue logic. The fine grainedstructure of FPGAs has been seen as being unsuitable forimplementing coarse grain algorithms. Moreover FPGAshave been touted as power hungry devices suitable for im-plementing control logic only.To overcome these disadvantages, CGRAs (CoarseGrained Reconfigurable Architectures) have been proposed[1]. CGRAs have advantages over conventional FPGAs interms of ease of reconfigurability and power consumption.Despite all these advantages, CGRAs have failed to makea mark in the industry. The failure can be attributed to thefactors like inflexibility, lack of unified design flow, com-mercial unavailability and lack of application domains.ASICs and GPPs (General Purpose Processors) lie at theextreme ends of flexibility versus performance graph. Thecurrent demand is for performance with increased flexibil-ity. FPGA lies in between ASICs and GPPs in the flexibility1-4244-0910-1/07/$20.00c2007 IEEE.versus performance graphs. One of the attractive features ofFPGA is the capability for dynamic and partial reconfigura-tion. There has been a lot of research to do partial dynamicreconfiguration on FPGA. Donthi and Haggard describe theextent of reconfigurability on the existing commercial FP-GAs [2]. Despite the popularity and inherent capabilityof FPGAs for partial reconfiguration, the vendors have notsupported it well commercially. Despite all the technologi-cal advances, run time reconfigurability is still hindered bythe lack of tool support from vendors and the long recon-figuration time [3]. Refer to [4, 3, 5] to read more aboutpartial run time reconfigurability on FPGA devices.QUKU is a coarse grained overlay for FPGA. The ideais to develop an architecture based on a proven and afford-able platform which doesnt have the inherent limitations ofthe underlying platform. The architecture has already beenpresented in [6, 7]. This paper aims in bringing out thedesign methodology of dynamic reconfiguration with andwithout using fine grained reconfiguration. We will also bediscussing the KPN network model applicability as a MoC(Model of Computation) and architecture to QUKU.The paper is formatted into following sections. The nextsection gives a short architectural overview of QUKU. Sec-tion3 describes the process network graphs and their anal-ogy to PE array. Section 4 covers the dual layered reconfig-urability feature of QUKU. Section 5 describes the designmethodology discussing the implementation details of a fewcommonly used DSP algorithms. Section 6 presents the re-sult followed by conclusion.2. QUKU ArchitectureQUKU is a merger of two technologies: CGRAs and FP-GAs. The aim is to develop a system which is based oncommercially available and affordable technologies but atthe same time provides active support for fast and efficientI$-OPBD$-OPBI-LMBD-LMBFSLOPBBRAMLMBLMBCoarse Grained PEarrayUser defined IPIP interfacecontrollerMicroblazeEMCFlash/ DDRSDRAMFPGAUARTRS232channelFigure 1. Block diagram of QUKUdynamic reconfiguration. This implementation will enableus to use the same platform for applications which are amix of control flow and computationally intensive applica-tions. Our system is unique in that it provides two levelsof application-specific reconfigurability. This dual level re-configurability is discussed in Section 4. QUKU is a com-plete SoC solution consisting of a coarse-grained PE matrixoverlaid on a FPGA. Fig. 1 shows a detailed block dia-gram of QUKU. The PE array is coupled with Microblazebased soft processor core using FSL (Fast Simplex Link).Microblaze is responsible for running software processesand scheduling algorithm. OPB (On-chip Peripheral Bus)is used to connect to peripherals like external memory con-trollers, UART, timer device and other user defined IP cores.2.1. Coarse Grain Programmable ArrayThe coarse gained programmable matrix consists of a dy-namically reconfigurable PE array, CMM and AMM. Referto fig. 2 for a block level description and acronyms. EachPE consists of a LCC and LAC besides containing a func-tional unit and a memory sub-system. CMM is responsi-ble for loading the configuration data onto the LCC of thePEs. AMM loads address parameters onto the LAC of thePEs. LAC controls read and write access to data and resultmemory of the respective PE. It also generates address foraccessing each memory.LCC - Local Configuration ControllerLAC - Local Address ControllerMU - Memory unitFU - Functional UnitCMM - Configuration Manager ModuleAMM - Address Manager ModuleCMMAMMLCCLACFUPEMUPE11PE12PE1nPEijPE21PEm1Figure 2. Block diagram of Coarse Grain PEArraya) Kahn process networkb)Dataflow process networkc)QUKUPE array process networkP1P2P3P4ProcessInfinite FIFO queueA1A2A3A4F2F3ActorFIFO queue12111Firing rulesPE1PE2PE3PE4FIFO Read RulesF1F2F3F4Read(F1,F4)Read(F1,F3).........Figure 3. Process Network diagrams2.2. PE Array OrganizationQUKU follows MIMD style architecture with distributedmemory. In MIMD, it is not feasible to provide a point-to-point connection between all PEs, especially for a large net-work of PEs. Hence a PE is connected to a fixed numberof neighboring PEs. Two of the commonly used topologiesare mesh and hypercube [8]. Hypercube has the disadvan-tage of requiring the number of PEs which is a power of 2.Although mesh based topology has no such limitation, thediagonal length is larger as compared to hypercube resultingin longer worst case interconnection delay.In any type of interconnection it is