FOUR BIT CARRY LOOK AHEAD ADDERAgendaAbstractIntroductionTheory of operationProject DetailsDESIGN FLOWPowerPoint PresentationSchematicLayoutLVS REPORTDFF timingsTest benchSimulation (clock period=5n)Simulations…Simulation (clock period=3.8n)Cost AnalysisLessons LearnedSummaryAcknowledgements1FOUR BIT CARRY LOOK AHEAD ADDERSUBMITTED BY:MILAN PATNAIKSHANTHI TENNETIDURGA L NALLARIADVISOR: PROF. DAVID PARENTDATE : 12-06-20042Agenda•Abstract•Introduction–why–Theory of operation•Project (Experimental) Details•Results•Cost Analysis•Conclusions3Abstract•We designed a 4-bit carry look ahead adder that operates at 263 MHz and uses 4.37W (3.06mW/sqcm) of Power and occupies an area of 404m x 353m4Introduction•Most widely used design for high speed adders. - explicit arithmetic operations - computing physical addresses in most modern CPUs. - used in digital systems where full fledged CPUs are superfluous. •Speed of various digital systems significantly influenced by speed of adders.5Theory of operation•Carry values calculated independently (determines carry ahead of time)•Propagate and Generate terms: Gi = Ai + Bi and Pi = Ai XOR Bi•Then outputs can be summarized as, Si=Pi xor Ci & Ci+1=Gi +PiCiC1:Previous carryC2 = G1 + P1C1 C3 = G2+P2G1+P2P1C1 C4=G3+P3G2+P3P2G1+P3P2PC1C5=G4+P4G3+P4P3G2+P4P3P2C2 1BIT FULL ADDER6Project Details•Initial hand calculations•Block level schematics•Block level layouts•Total schematic•Integration of the block level layouts•Circuit extraction & LVS•Post extraction simulations7DESIGN FLOW8Cg of Driver MUX (master ff)= 19.93fF which matches the Cg =20fF assumption.9Schematic10Layout11LVS REPORT12DFF timingsT hold (rise)=0.5nT hold (fall)=0.48nT setup (rise)=0.73nT setup (fall)=0.64n13Test bench14Simulation (clock period=5n)15Simulations…Period= 4nsPeriod=3.5ns16Simulation (clock period=3.8n)17Cost Analysis•Time spent on the various phases of the project:–verifying logic(2 days)–Hand calculations(1 week)–Layout(4 days)–Modifying layout(2 days)–post extracted simulations(1 day)18Lessons Learned•Start working as early as possible!!•Plan the layout beforehand for an efficient design.•Use the same cell heights for all the blocks.19Summary•Our CLA operates at 263 MHz of Clock Frequency, uses 4.37W of Power and occupies an area of 404m x 353m•The adder can be designed with lesser area and power consumption with a more organized Layout20Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Synopsys for Software donation•Thanks to Professor David Parent•Thanks to EE166
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