FAN5098Two Phase Interleaved Synchronous BuckConverter for AMD HammerByEd TorrenteEE136Table of ContentsIntroduction…………………………………………………………………….. Pg. 3Circuit Operation and Capabilities...………………………………………….. Pg. 4Component Selection and Implementation.…………………………………... Pg. 6Test Results………………………………………………………………………. Pg. 7Conclusion………………………………………………………………………… Pg. 8References………………………………………………………………………… Pg. 9Dr. D ZhouPower Electronics4 December 20022IntroductionIt is becoming more evident that technology is moving towards low voltage applications. For example, Francisco Maloberti from Texas A&M developed a voltage regulator that outputs a reference voltage within the range of 500mV to 530mV over 1V of power supply voltage. Moreover, today’s microprocessor requires not only operation in the milivolt range but the use of less passive components is ideal thus reducing headroom in the entire circuit.On November 6, 2002 Fairchild Semiconductor announced a voltage regulator IC, FAN5098 for the AMD Hammer processors. The function of the FAN5098 is to give accurate, proficient power regulation for the CPU VCORE in desktop, workstation and server applications. The FAN5098 utilizes a multi-phase design that includes a distinctive control-loop method which better facilitates load regulation and transient response time.The two-phase FAN5098 has built-in, high performance MOSFET drivers along with a 5-bit VID codes that allow for output ranges of 800mV-1.550V. Active VID transitions are sustained per AMD conditions with no glitch output voltage and controlled slew-rate. Typical output current is 40A and can easily scaled, enabling flexible motherboard designs to support future AMD processors. The current is sensed through loss-less MOSFET RDS(on) techniques and the current is matching is being managed between the output phases.Programmable Active Droop facilitates the use of less capacitors while transient voltage regulation requirements are met. Loop compensation is designed internally thus reducing externalcomponents and cost. Over-voltage/under-voltage protection, programmable current limiting, programmable soft-start, thermal protection and power-good output are built-in features to increase safety and reliability.Dr. D ZhouPower Electronics4 December 20023Circuit OperationThe FAN5098 controller is a programmable synchronous multi-phase DC-DC capable of delivering 40A of output current when it is appropriately designed with the proper components (specifically designed for the AMD Hammer). Moreover, it functions as a PWM step down regulator with high efficiency mode (E*) at light load.The main control loop has two interleaved synchronous buck converters with summing mode control. Interleaved, which means that the two buck converters run 180° out of phase with each other which minimizes the RMS input current ripple which in turn curtails the amount of input Dr. D ZhouPower Electronics4 December 20024capacitors that is necessary. Furthermore, the interleaved design doubles the effective frequency thus improving transient response. The summing Mode control provides superior performance by allowing a large converter bandwidth over a wide range of output loads and external components.Hence, no external component is required.The control loop has an analog as well as digital control blocks. The analog consists of comparators feeding into signal conditioning amplifiers providing the input to the digital control block. The signal conditioning section then accepts inputs from a current sensor and a voltage sensor, with the voltage sensor being common to both phases, and a current sensor separate from each. Once this is accomplished, the voltage sensor amplifies the difference between VFB signal and the reference voltage from the DAC and presents the output to each of the two signal conditioning amplifiers. The current control path for each phase then takes the difference betweenPGND and SW pins when the low-side MOSFET is on thus reproducing the voltage across the MOSFET, hence the input current. This represents the resulting signal to the same input of its summing amplifier, adding its signal to the voltage amplifiers which has a certain gain and resulting in the two signals being added. This sum is then showed to the signal conditioning blocks looking into the oscillator ramp, which provides the main PWM control signal to the digital control block. The oscillator ramps are 180° out of phase from each other such that the twophases are on alternately. Finally, the digital control block takes the analog signal from the Dr. D ZhouPower Electronics4 December 20025Block ABlock Bconditional blocks to provide the appropriate pulses to the HDRV and LDRV output pins for each phase. These outputs control the external block.The response time used by the controller is the leading-edge control instead of the trailing-edge. The leading-edge control turns the high-side MOSFET on when the error amplifier output voltageis equal to the ramp voltage and turns it off at the clock signal resulting in rapid response by the FAN5098 by turning on the high-side MOSFET when the transient occurs as oppose to trailing-edge where the high-side MOSFET is turned on at the clock signal and turns off when the error amplifier output voltage is equal to the ramp voltage. As a result, the response time of the trailing-edge converter can be as long as the off-time of the high-side driver, nearly an entire switching period. The response time is set by the internal propagation delay which is typically 100ns and the worst case response time corresponds to the minimum on-time of the low side MOSFET of 300ns. The IC also has remote voltage sense capability which eliminates errors due to trace resistance.The output drivers consist of high current capacity that uses MOSFETs which is configured in a push and pull configuration. The drivers for the high-side MOSFET use the BOOT pin for input power and the SW pin for the return whereas the drivers for the low-side MOSFET uses the VCC pin for input power and PGND pin for return. Typically, the BOOT pin will use a charge pump and the BOOT and VCC pins are separated from the chip’s internal power and ground, BYPASS