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UCSD CSE 143 - Designing with the Nios II Processor and SOPC Builder

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Designing with the Nios II Processor and SOPC Builder Exercise Manual Software Requirements: Quartus II 8.1 ModelSim 6.3g (for Quartus II 8.1) Nios II 8.1 Altera Megacores IP 8.1 Hardware Requirements: This lab guide is set up to allow you to use the following boards: Nios Development Kits: Stratix 1S10 and 1S10ES Stratix 1S40 Stratix II 2S60 and Stratix 2S60ES Cyclone 1C20 Cyclone II 2C35 and 2C35ES Cyclone III Starter FPGA and Nios II Embedded Evaluation Kits (NEEK) Lead-Free (rohs) Kits: Stratix II 2S60 and Stratix 2S60ES Cyclone II 2C35 and 2C35ES Cyclone III FPGA Starter Kit Cyclone III Nios II Evaluation (NEEK) Kit DSP Development Kits: Stratix II 2S60 and 2S60ESExercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation A-MNL-NIIHW-EX-8-1-v1 2Exercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation A-MNL-NIIHW-EX-8-1-v1 3 Lab 1 Creating a Nios II Processor SystemExercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation A-MNL-NIIHW-EX-8-1-v1 4Exercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation A-MNL-NIIHW-EX-8-1-v1 5 Objectives: Over the course of the lab today, you will create an embedded hardware system and run some software code on it. As the lab progresses, you will continue to modify your hardware system to incorporate new features as you learn about them in class. This lab guide is set up to allow you to use any one of the following development kits, so, some written steps will pertain to one type of board; other steps to another type of board. You can tell when type of kit your are using by looking at the labelling on the FPGA package on your kit. Failing that, the instructor should be able to advise you. The kits fall into two main categories as shown below: Nios II Processor Development Kits: Stratix Stratix II Stratix 1S10 Stratix II 2S60 Stratix 1S10ES Stratix II 2S60ES Stratix 1S40 Stratix II 2S60 rohs (new lead-free kit) Cyclone Cyclone II Cyclone III Cyclone 1C20 Cyclone II 2C35 FPGA Starter Kit Cyclone II 2C35ES Nios II Evaluation (NEEK) -and- DSP Development Kits: Stratix II Stratix II 2S60 2S60ES Note: It is unlikely that you will using a DSP kit unless you are also taking the DSP class.Exercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation A-MNL-NIIHW-EX-8-1-v1 6 Step 1: Set Up Embedded Hardware Design Project Hardware set up requirements: • USB-Blaster, ByteBlaster, ByteBlaster II, or Byte Blaster MV programming cable connected between computer and JTAG connection header on development board • Power supply connected to the board Typical Nios II Processor Development Kit 1. Insert the CD Rom from the back of your handout into the computer provided. 2. Open the CD Rom for viewing, and double-click on the .exe file you see. It will be called “NII_SOPCBuilder_2Day_<ver>.exe.” This is a self-extracting zip file that will unzip the files you need for today into the folder called, C:\altera_trn\Nios II_HW\NiosII_2Day. 3. Navigate into that directory and then into Day1. In this directory, you will find several sub-directories for each of the different types of development boards supported for this class. Inside each respective project folder is a sub-directory called niosII_lab that contains the partially completed Quartus II project that you will use as your starting point today. Note: Do not connect LCD display to board even though it is shown in the figure – you will not be using it today.Exercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation A-MNL-NIIHW-EX-8-1-v1 7 4. Navigate into the appropriate project folder for your particular development kit: (Refer to the illustrated directory structure below for help or consult instructor.) You will have to check the part on your board to confirm this. Also, please note whether your part ends with ES or not or whether it is a Rohs kit. Lab Directory Structure and Working Area for Stratix II 2S60ES kit Nios II Processor Development Kit 5. Change directory into nios_II_lab located inside your particular kit’s project folder. Start the Quartus II Software by double-clicking on the project file located therein: (ie. niosII_lab.qpf) DSP Kits Folder Nios Kits FoldersExercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation A-MNL-NIIHW-EX-8-1-v1 8 6. Assign device family and pinout settings to your Quartus II project by sourcing the TCL script provided in your working directory (see over). From the Tools menu select Tcl Scripts, and then from the Project folder choose the setup script for your development board (eg. Setup_Cyclone_2C35.tcl, etc.), and click Run. This will automatically assign the relevant device settings and pin-outs to the Quartus II project for the particular FPGA development board you are using. If you are unsure about which kit you are using, please check FPGA on development board or consult your instructor. Note: As an alternative, you may also source the Tcl script from the Tcl command prompt in Quartus II by typing “source” followed by the name of the script. For example: “source Setup_StratixII_2S60_rohs.tcl”. 7. Save your updated project settings: File > Save Project. 8. Next, you will start building your embedded system: It will be composed of the following components: Nios II CPU Tightly-coupled on-chip instruction memory External SRAM or SSRAM memory controller External Flash memory controller One or more tri-state bridge components to interface with the memory components on the tri-state bus or busses on your board JTAG UART peripheral (cont. over)Exercise Manual Designing with the Nios II Processor & SOPC Builder (Day 1) Copyright © 2008 Altera Corporation


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UCSD CSE 143 - Designing with the Nios II Processor and SOPC Builder

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