l 1 Introduction to Embedded Systems Chapter 10: Interrupts Edward A. Lee Alberto Sangiovanni-Vincentelli UC Berkeley EECS 149/249A Fall 2014 Lee & Seshia, UC Berkeley: 2 Input/Output Mechanisms in Software ¢ Polling l Main loop uses each I/O device periodically. l If output is to be produced, produce it. l If input is ready, read it. ¢ Interrupts l External hardware alerts the processor that input is ready. l Processor suspends what it is doing. l Processor invokes an interrupt service routine (ISR). l ISR interacts with the application concurrently.l 2 Lee & Seshia, UC Berkeley: 3 Polling Processor Setup Code Processor checks I/O control register for status of peripheral 1 Processor services I/O 1 Processor checks I/O control register for status of peripheral 2 Processor checks I/O control register for status of peripheral 3 Processor services I/O 2 Processor services I/O 3 Ready Ready Ready Not Ready Not Ready Not Ready Lee & Seshia, UC Berkeley: 4 Recall Using a Serial Interface In an Atmel AVR 8-bit microcontroller, to send a byte over a serial port, the following C code will do: while(!(UCSR0A & 0x20)); UDR0 = x; • x is a variable of type uint8. • UCSR0A and UDR0 are variables defined in header. • They refer to memory-mapped registers in the UART.l 3 Lee & Seshia, UC Berkeley: 5 Send a Sequence of Bytes for(i = 0; i < 8; i++) { while(!(UCSR0A & 0x20)); UDR0 = x[i]; } How long will this take to execute? Assume: • 57600 baud serial speed. • 8/57600 =139 microseconds. • Processor operates at 18 MHz. Each while loop will consume 2500 cycles. Lee & Seshia, UC Berkeley: 6 Input Mechanisms in Software ¢ Polling l Main loop uses each I/O device periodically. l If output is to be produced, produce it. l If input is ready, read it. ¢ Interrupts l External hardware alerts the processor that input is ready. l Processor suspends what it is doing. l Processor invokes an interrupt service routine (ISR). l ISR interacts with the application concurrently.l 4 Lee & Seshia, UC Berkeley: 7 Interrupts ¢ Interrupt Service Routine Short subroutine that handles the interrupt Processor Setup Code Register the Interrupt Service Routine Processor executes task code Run Interrupt Service Routine Interrupt! Context switch Resume EECS 149, UC Berkeley: 8 Interrupts Triggers: ¢ A level change on an interrupt request pin ¢ Writing to an interrupt pin configured as an output (“software interrupt”) Responses: ¢ Disable interrupts. ¢ Push the current program counter onto the stack. ¢ Execute the instruction at a designated address in the flash memory. Design of interrupt service routine: ¢ Save and restore any registers it uses. ¢ Re-enable interrupts before returning from interrupt. Source: ATmega168 Reference Manual Program memory addresses, not data memory addresses.l 5 EECS 149, UC Berkeley: 9 Berkeley Microblaze Personality Memory Map 0xFFFFFFFF 0x0000004F 0x0000FFFF Unmapped(Area(ADC(subsystem(Memory(for(Instruc7ons(and(Data((Interrupt(controller(0x81800000 MicroBlaze(50MHz(MEMORY(BRAM(UART0(UART1(ADC(Subsystem(TIMER(Debugger(Interrupt(controller(0x8180FFFF Unmapped(Area(Timer(0x83C00000 0x83C0FFFF Unmapped(Area(UARTs(Unmapped(Area(0x84000000 0x8402FFFF Debugger(Unmapped(Area(Unmapped(Area(0x84400000 0x8440FFFF 0xC2200000 0xC220FFFF Reset,(interrupt,(…(0x00000000 EECS 149, UC Berkeley: 10 Microblaze Interrupt Policy • “The interrupt return address (the PC associated with the instruction in the decode stage at the time of the interrupt) is automatically loaded into general purpose register R14.” • “In addition, the processor also disables future interrupts by clearing the IE [Interrupt Enable] bit in the MSR [Machine Status Register]. The IE bit is automatically set again when executing the RTID instruction.” Source: Microblaze datasheetl 6 EECS 149, UC Berkeley: 11 Timed Interrupt Timer Update Tick / Sample When timer expires, interrupt processor Reset timer Processor jumps to ISR Resumes Processor Setup Register Interrupt Service Routine Initialize Timer Execute Task Code EECS 149, UC Berkeley: 12 Example: Set up a timer on an ATmega168 to trigger an interrupt every 1ms. ¢ TCCR: Timer/Counter Control Register ¢ OCR: output compare register ¢ TIMSK: Timer Interrupt Mask The “prescaler” value divides the system clock to drive the timer. Setting a non-zero bit in the timer interrupt mask causes an interrupt to occur when the timer resets. Source: iRobot Command Module Reference Manual v6l 7 EECS 149, UC Berkeley: 13 Setting up the timer interrupt hardware in C #include <avr/io.h> int main (void) { TCCR1A = 0x00; TCCR1B = 0x0C; OCR1A = 71; TIMSK1 = 0x02; ... } This code sets the hardware up to trigger an interrupt every 1ms. How do we handle the interrupt? Source: ATmega168 Reference Manual memory-mapped register. But how is this proper C code? EECS 149, UC Berkeley: 14 void initialize(void) { cli(); // Set I/O pins DDRB = 0x10; PORTB = 0xCF; ……. // Set up timer 1 to generate an interrupt every 1 ms TCCR1A = 0x00; TCCR1B = (_BV(WGM12) | _BV(CS12)); OCR1A = 71; TIMSK1 = _BV(OCIE1A); // Set up the serial port with rx interrupt ……. // Turn on interrupts sei(); } // Global variables volatile uint16_t timer_cnt = 0; volatile uint8_t timer_on = 0; // Timer 1 interrupt to time delays in ms SIGNAL(SIG_OUTPUT_COMPARE1A) { if(timer_cnt) { timer_cnt--; } else { timer_on = 0; } } void delayMs(uint16_t time_ms) { timer_on = 1; timer_cnt = time_ms; while(timer_on) ; } //Enable interrupts (interrupt.h) # define sei() __asm__ __volatile__ ("sei" ::) //Disable interrupts (interrupt.h) # define cli() __asm__ __volatile__ ("cli" ::) #define SIGNAL(signame) \ void signame (void) __attribute__ ((signal)); \ void signame (void) #define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr)) #define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + 0x20) #define _SFR_MEM8(mem_addr) _MMIO_BYTE(mem_addr) #define _BV(bit) (1 << (bit)) //Timer defines (iomx8.h) #define TCCR1A _SFR_MEM8 (0x80) #define TCCR1B _SFR_MEM8 (0x81) /* TCCR1B */ #define WGM12 3 #define CS12 2l 8 EECS 149, UC Berkeley: 15 Setting up the timer interrupt hardware in C #include