MASON CS 365 - Instruction Set Architectures

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Instruction Set Architectures CS 365 Lecture 2 Prof Yih Huang CS 365 1 Instruction Set Architecture Definition Data types and structures Encoding and representation Instruction set Instruction format Addressing modes accessing data and instructions Exception conditions CS 365 2 1 Examples IBM 360 370 Motorola PowerPC DEC VAX Alpha HP PA RISC Sun Sparc SGI MIPS Intel X86 CS 365 3 Registers Registers are a small set of storage cells inside the processor MIPS provides 32 x86 provides 8 for arithmetic Registers are directly accessible through machine instructions Registers are much much faster than memory CS 365 4 2 MIPS Registers Name Register Usage zero 0 The constant value 0 at 1 By assembler only vo v1 2 3 Values for results and expression evaluation a0 a3 4 7 Arguments t0 t7 8 15 Temporaries s0 s7 16 23 Saved t8 t9 24 25 More temporaries k0 k1 26 27 Reserved for the operating system gp 28 Global pointer sp 29 Stack pointer fp 30 Frame pointer ra 31 Return pointer CS 365 5 Discussion Usages are software conventions They are not built into the hardware Except registers 0 and 31 all others are treated the same by the hardware Register 0 is hardwired 0 Writing to it will not changed its value Register 31 is implied in the jal instruction CS 365 6 3 MIPS Arithmetic All instructions have 3 operands all of them registers Example C code A B C D E F A MIPS code add t0 s1 s2 add s0 t0 s3 sub s4 s5 s0 Variables must be moved between registers and memory before and after computation CS 365 7 Arithmetic Instruction Format opcode rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits opcode 000000 rd rs funct rt Functions see the third table of Fig 3 18 ADD SUB MULT DIV Signed Unsigned AND OR XOR NOR Set On Less Signed Unsigned We ignore shamt shift amount for now CS 365 8 4 Exercises add t0 s1 s2 000000 10001 10010 01000 00000 100000 opcode rs rt rd shamt funct rt rd shamt funct xor a2 t8 v0 opcode rs CS 365 9 Arithmetic with Immediates opcode rs rt 6 bits 5 bits 5 bits Immediate 16 bits opcode 001XXX rt rs op Immediate XXX determines operations addi addiu add immd signed unsigned andi ori xori lui Load Upper Immediate See the 2nd row in 1st table of Fig 2 25 CS 365 10 5 Exercises add t1 s3 10 001000 10011 01001 XXX 000 rs s3 rt t1 0000000000001010 Immediate 10 add t1 s3 10 001000 10011 01001 XXX 000 rs s3 rt t1 Immediate 10 CS 365 11 Load 32 bit Constants Example to load the number below into s0 00000000 00111101 00001001 00000000 61 2304 Step 1 lui s0 61 opcode 001111 The value of s0 becomes 00000000 00111101 00000000 00000000 Step 2 addi 0 s0 2304 CS 365 12 6 Memory A set of data entries indexed by addresses Typically the basic data unit is byte In 32 bit machines 4 bytes grouped to words Have you seen the DRAM chips in your PC 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F CS 365 13 Where Are the Variables Each variable has a home in memory A particular location in the memory is assigned to store the content of the variable The address of a variable is determined by The compiler in high level languages You if you do machine programming Variables are moved from memory to registers before computations CS 365 14 7 Example C A B Memory 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F Processor S0 S1 S2 A B Registers C CS 365 15 Discussions Registers are part of the processor Fast but limited in numbers Memory is slooooooooooooooooooow For best performance Use registers for important data Minimize the traffic to from memory CS 365 16 8 Load and Store Instructions Move data between memory and registers Example C code A 7 h A 8 MIPS code lw t0 32 s3 add t0 s2 t0 sw t0 28 s3 Store word sw has destination last CS 365 17 Instruction Format opcode rs rt 6 bits 5 bits 5 bits Offset 16 bits Load opcode 100XXX rt Memory rs Offset Store opcode 101XXX Memory rs Offset rt XXX determines data sizes byte half word word See the 5th and 6th rows in 1st table of Fig 2 25 CS 365 18 9 Example lw t2 24 s3 100011 10011 01010 XXX 011 rs s3 0000000000001100 rt t2 Offset 24 rt sp Offset 8 sw v1 8 sp XXX rs v1 CS 365 19 Stored Program Concept Instructions are bits Programs are stored in memory just like data How does the processor distinguish instructions from data It does not until recently AMD64 does make the distinction CS 365 20 10 Instruction Execution Cycles A special register called Program Counter PC points to the address of the next instruction for execution CPU reads from memory the instruction pointed by PC The control logic makes the designated function carried out PC is increased to point to the next instruction PC 4 in the case of MIPS CS 365 21 Example Assembly Instructions lw t2 24 s3 add s0 s1 s2 Machine instructions in memory 1004 10001110 01101010 00000000 00001100 1008 00000010 00110010 10000000 00100000 CS 365 22 11 Example Continued Memory Processor 1004 1008 10001110 01101010 00000000 00001100 00000010 00110010 10000000 00100000 S0 S1 S2 Registers 00001004 PC CS 365 23 Control Instructions Sequential execution is achieved by increasing PC 4 Non sequential executions If switch loops in C Need to give a different next instruction address other than PC 4 Control instructions update the PC They are also called branch instructions for they allow the processor to branch from the default execution path CS 365 24 12 Conditional Braches MIPS conditional branch instructions bne t0 t1 Label beq t0 t1 Label Example if i j h i j bne s0 s1 Label add s3 s0 s1 Label CS 365 25 Instruction Format opcode rs rt 6 bits 5 bits 5 bits Offset 16 bits opcode 000XXX where XXX 000 PC PC Offset if test condition true Test conditions XXX 100 rs rt beq XXX 101 rs rt bne XXX 110 rs 0 blez XXX 111 rs 0 bgtz CS 365 26 13 Unconditional Branches Assembly j label opcode 26 bit Immediate Action CS 365 27 Control MIPS unconditional branch instructions j label Example if i j h i j else h i j CS 365 beq s4 s5 Lab1 add s3 s4 s5 j Lab2 Lab1 sub s3 s4 s5 Lab2 28 14 Exercise Give the machine instruction of the beq in the previous page CS 365 29 Supporting Procedure Calls F G G H H Observe the control flow thru the 3 proc Need machine instructions to remember the return point CS 365 30 15 JAL Jump and Link Jump to address of procedure while storing the return address PC 4 in register 31 …


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