Final Exam Review B Ramamurthy Date Time and Place Date Tuesday May 5 2009 Time 8 00 11 00AM Place Filmore 170 Please bring pens pencils calculator with no prior stored data we will check it You are allowed two A 4 Copier paper size sheets of any information you feel will be useful for answering the questions Reading material Chapter 5 Processor design datapath and control design Chapter 4 Assessing and Understanding performance Chapter 6 Enhancing performance with pipelining Chapter 7 Cache for performance exploiting memory hierarchy for performance All the class notes Exercises at the end of the chapters Specific Sections 4 1 4 3 example on page 268 269 exercises we worked out in the class see the list on lecture schedule 5 2 5 4 Class notes we will review some exercises 6 1 6 6 class notes we will work some examples in class 7 1 7 3 class notes we will work on exercises at the end of the chapterbi Possible questions Performance evaluation CPI MIPS rating clock rate comparison Single cycle datapath and control design Pipeline design adding buffers and control circuits for the buffer Branch prediction circuit verilog design Cache design organization direct associative performance improvement Format Word problems to math equations and evaluations Verilog design Adding buffer and digital circuits Multiple choice on datapath