VHDL TutorialCMSC 711 CADENCE TUTORIAL Dr. Jim PlusquellicPrepared by :- Chintan Patel Page 1VHDL Tutorial This tutorial will cover the steps involved in compiling, elaborating and simulating VHDLdesign files. The NC-simulator and the ncvhdl compiler under the cadence distribution will beused for this purpose. This tutorial will cover only the command line option of running all thesetools. A later tutorial will cover the GUI option for the same.The ncvhdl and nc-simulator binaries live under a different directory structure than the normaldirectory structure used by the icfb and other related tools in the cadence distribution. So you willrequire a separate .cshrc file to run these tools. The file is available at the class webpage and iscalled .cshrc.sim. Copy the file in your home directory and source it whenever you want to runVHDL simulations. The command for this is source .cshrc.sim. Source the normal .cshrc fileusing the command source .cshrc when you want to run any other tools except the nc-simulatorsand compilers. You will have to source one of the two files whenever you switch form icfb toncvhdl and vice versa. Next step is to copy some options files and setup a directory structure. It is important that youfollow the steps involved in setting up the directory structure so that your designs are compatiblewith the GUI options. Change your directory to cadence using cd cadence. Then make a directorycalled vhdl in the cadence directory using mkdir vhdl. Change your working directory to vhdlusing cd vhdl. Now you will have to copy two files into this directory. One is the cds.lib file thatdefines the path to some standard vhdl libraries and the hdl.var file that list the options required bythe simulator for proper operation. They are available on the course webpage and a copy is pro-vided below. Copy these files into your vhdl directory and make sure that they have the followinglines.cds.lib file :-- -- - This cds.lib file is made specifically to be used with the ldv toolset- -DEFINE ieee /cds/ldv/tools.sun4v/inca/files/IEEEDEFINE std /cds/ldv/tools.sun4v/inca/files/STDDEFINE vhdl /home/grad2/cpatel2/cadence/vhdlChange the path in the last line to point to your vhdl directory. So you will have something likeyour_home_directory/cadence/vhdl in the last line.hdl.var file :-DEFINE WORK vhdlAfter you have copied these files in your vhdl directory you are ready to enter vhdl code. Thistutorial will cover the design and simulation of an inverter in VHDL. The directory structure thatis explained in this tutorial should be implemented for each design. The only difference will bethe names of the respective directories depending on your design names.CMSC 711 CADENCE TUTORIAL Dr. Jim PlusquellicPrepared by :- Chintan Patel Page 2We will start by making a directory called inverter in the vhdl directory. Then create a directorycalled vhdl under the inverter directory. The commands required for the above steps are shownhere.mkdir invertercd invertermkdir vhdlcd vhdlNow make a file called vhdl.vhd under the vhdl directory and type in your VHDL code in thisfile. The code for the inverter is shown below and is also available on the course webpage. Theemacs editor under sunserver1 has a special vhdl options menu when you edit any .vhd file. Thiswill be a great help when learning VHDL and most of the default VHDL statements are present inthe menu. Note that when you write you VHDL code for the inverter the entity is called inverterwhich is the same name that you used for the directory. Please name the top level entity in yourdesign the same as the directory that it lives in. Please look at the comments in the code below forinformation about the specifics.vhdl.vhd file for the inverter.- -- - Entity: inverter- - Architecture : structural- - Author: cpatel2- - Created On: 10/20/00 at 13:32- --- These are the standard libraries that you are defining.library IEEE;use IEEE.std_logic_1164.all;-- The entity name should be same as the directory name that you are designing in.-- Ports are the inputs and outputs from your circuit.entity inverter isport (input : in std_logic;output : out std_logic);end inverter;-- Define an architecture for the inverter entity which is either functional or behavioral.architecture structural of inverter isbegin-- Concurrent assignment statement. output <= not (input);end structural;CMSC 711 CADENCE TUTORIAL Dr. Jim PlusquellicPrepared by :- Chintan Patel Page 3 Now before we go on to compiling and simulating we need to make a test bench to test thecode that we just entered. A test bench is another VHDL file that uses your design file and gives itinputs and checks the outputs. The input and output is done using text files through the VHDLcode using inbuilt I/O functions. For making a test bench make are directory called inverter_testin your ~/cadence/vhdl directory. Then make a vhdl directory under the inverter_test directory thesame way as you did for the inverter. Inside the inverter_test/vhdl directory make a file calledvhdl.vhd and enter the code for you test bench in it. The test bench file is available on the coursewebpage and is also shown below. Again the entity should have the same name as the directoryyou are designing in. The color formatting is not shown here as in the previous case but will bepresent if you use the emacs editor.vhdl.vhd file for the test bench.- -- - Entity: inverter_test- - Architecture : vhdl- - Author: cpatel2- - Created On: 10/20/00 at 01:55- -- - Define the libraries that you are going to use. The two textio libraries define your input and- - output functionslibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_textio.all;use STD.textio.all;- - The entity name here is also the name as the directory that you are designing in.- - The circuit has no ports because this is a test bench file that you are using to test the inverter.entity inverter_test isend inverter_test;- - Define an architecture for the inverter_test entity.architecture test of inverter_test is- - Define the inverter as a component that you will use in this file. The port list is the same as- - the original port list of the inverter entity.component inverter port ( input : in std_logic; output : out std_logic);end