G22.2233 L01 Introduction.1 Banikazemi, NYU, 2007CS G22.2233 Computer Systems Design Spring 2007Lecture 01: IntroductionMohammad Banikazemi[Slides from Prof. Mary Jane Irwin, PSU Adapted fromComputer Organization and Design, Patterson & Hennessy, © 2005, UCB]G22.2233 L01 Introduction.2 Banikazemi, NYU, 2007Course Administration Instructor: Mohammad Banikazemi [email protected] Professor, NYUResearch Staff Memebr, IBM T. J. Watson Research Center401 WWH BuildingOffice Hrs: W 7:00-8:00pmText: Required: Computer Org and Design, 3rd Edition, Patterson and Hennessy ©2005 URL: www.cs.nyu.edu/courses/spring07/G22.2233-001/Slides: pdf on the course web page after lectureG22.2233 L01 Introduction.3 Banikazemi, NYU, 2007Let’s Get Started Motivation Course organization Administrative stuffO workload and grading Brief overview of SimpleScalar toolset Introduction to Computer DesignO Target marketsO Technology trends Instruction Set Architecture[Patterson/Hennessy COD: HSI (3rdEdition): Chapters 1 and 2]G22.2233 L01 Introduction.4 Banikazemi, NYU, 2007PC Motherboard CloseupProcessorI/O busslotsProcessorinterfaceGraphicsinterfacesDisk&USBMemoryCPUComputerControlDatapathMemory DevicesInputOutputG22.2233 L01 Introduction.5 Banikazemi, NYU, 2007From the Intel 386 to the Pentium 4Intel 386, introduced 1985275,000 transistors, 1 micron16 MHz clock speedIntel Pentium III, introduced 19999.5M transistors, 0.25 micron600 MHz clock speedIntel 4 Prescott, introduced late 04125M transistors, 0.09 micron2.8-3.8 GHz clock speedG22.2233 L01 Introduction.6 Banikazemi, NYU, 2007Intel Pentium III MicroarchitectureROBL2 cacheIDIFUDCUDTLBITLBBTBMISRSSIMDRATIEUFEUMIUMOBIFU: Instruction fetch unitID: Instruction dispatchMIS: Micro-instruction sequencerBTB: Branch target bufferRAT: Register alias tableRS: Reservation stationIEU: Int. execution unitFEU: FP execution unitDCU: Data cache unitROB: Reorder BufferMOB: Memory OrderingBufferMIU: Mem Interface unitG22.2233 L01 Introduction.7 Banikazemi, NYU, 2007How Do the Pieces Fit Together?I/O systemInstr. Set Proc.CompilerOperatingSystemApplicationDigital DesignCircuit DesignInstruction SetArchitectureFirmware Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluationMemory systemDatapath & Control G22.2233 L01 Introduction.8 Banikazemi, NYU, 2007Course Content ContentO Principles of computer architecture: CPU datapath and control unit design (single-issue pipelined, superscalar, VLIW), memory hierarchies and design, I/O organization and design, and introduction to advanced processor design (multiprocessors and SMT) Course goalsO To learn the organizational paradigms that determine the capabilities and performance of computer systems. To understand the interactions between the computer’s architecture and its software so that future software designers(compiler writers, operating system designers, database programmers, …) can achieve the best cost-performance trade-offs and so that future architects understand the effects of their design choices on software applications.G22.2233 L01 Introduction.9 Banikazemi, NYU, 2007What You Should Be Familiar With  Basic logic design & machine organizationO Bits, gates, combinational and sequential logic Create, assemble, run, debug small programs in an assembly language Create, compile, and run C programs Create, organize, and edit files and run programs on Unix/LinuxG22.2233 L01 Introduction.10 Banikazemi, NYU, 2007Course Structure Design focused classO Various homework assignments throughout the semesterO Simulation of architecture alternatives using SimpleScalar Lectures:O 3-4 weeks review of the MIPS ISA and basic architecture O 4-5 weeks pipelined datapath design issues and superscalarO 2 week memory hierarchies and memory design issuesO 2 weeks I/O design issuesO 1 week introduction to multiprocessor design issuesO 1 week examsG22.2233 L01 Introduction.11 Banikazemi, NYU, 2007Course Workload Lectures (Reading assignments from text)O Text: Computer Org and Design, 3rd Edition, Patterson and Hennessy ©2005 Lab and Homework assignmentsO Programming assignments - Building a simulator for a modern processor- Use this simulator to understand impact of architectural techniquesO Homework assignments Midterm exam  Final examO Review and sample questions will be provided in classAcademic misconduct taken very seriouslyhttp://www.cs.nyu.edu/web/Academic/Graduate/academic_integrity.htmlG22.2233 L01 Introduction.12 Banikazemi, NYU, 2007Grading Information Grade determinatesO Midterm Exam ~30%- Wed. March 21, 5:00-6:50pm, WWH 1013 O Final Exam ~40%- Wed. May 2, 5:00-6:50pm, WWH 10 O Homework and lab assignments ~30%- Homework assignments due at the beginning of class - Code to be submitted electronically by 17:00 on the due date)-No lateassignments will be accepted.G22.2233 L01 Introduction.13 Banikazemi, NYU, 2007SimpleScalar Toolset Comprehensive collection of tools for evaluating new architectural techniquesO Possible to define new instruction-set architectures (support for Alpha, PISA)O Modules for writing own execution-driven simulators- bpred, caches, statistics collection, program loading, functional unit construction, …O Many papers at recent architecture conferences use SimpleScalarSimulatorCoreG22.2233 L01 Introduction.14 Banikazemi, NYU, 2007SimpleScalar Toolset (cont’d) For the course assignments we will be using a small subset of the toolsO You will be using an instructional ISA called PISA- Closely resembles MIPS 64O PISA executables produced using GNU cross-compiler tools Goal of the assignments: To understand the issues involved in implementing and to assess the potential benefits from architectural techniques used in modern-day microprocessorsO E.g., Branch prediction in modern-day microprocessors- At what stage during instruction execution is branch prediction used?– It takes some time to figure out that an instruction is a branch- How should the branch predictor be updated with information about seen branches?- What impact does prediction have on performance?G22.2233 L01 Introduction.15 Banikazemi, NYU, 2007Outline Motivation Course organization Administrative stuffO workload and grading Brief overview of SimpleScalar toolset Introduction to Computer DesignO Target marketsO Technology trends Instruction Set Architecture[Patterson/Hennessy