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Where we are headedMulticycle ApproachReview: finite state machinesSlide 4Slide 5Multicycle Datapath with control signalsMulticycle Datapath & ControlFive Execution StepsHigh level view of finite state machine controlStep 1: Instruction FetchStep 2: Instruction Decode and Register FetchInstruction Fetch & DecodeStep 3 (instruction dependent)Step 4 (R-type or memory-access)Write-back stepFinite state machine for memory access instructionsFinite state machine for R-format instructionsFinite state machine for branch instructionFinite State Machine for jumpSummary:Complete Finite State MachineSimple QuestionsExceptionsHow are exceptions handled?Exception handlingDatapath & Control with support for exceptionsException HandlingSlide 28States for handling exceptionsComplete FSM including support for exceptionsImplementing the ControlGraphical Specification of FSMFinite State Machine for ControlPLA ImplementationROM ImplementationSlide 36ROM vs PLAThe Big Picture1Where we are headed•Single Cycle Problems:–what if we had a more complicated instruction like floating point?–wasteful of area•One Solution:–use a “smaller” cycle time–have different instructions take different numbers of cycles–a “multicycle” datapath:PCMemoryAddressInstructionor dataDataInstructionregisterRegistersRegister #DataRegister #Register #ALUMemorydata registerABALUOut2•We will be reusing functional units–ALU used to compute address and to increment PC–Memory used for instruction and data•Our control signals will not be determined solely by instruction–e.g., what should the ALU do for a “subtract” instruction?•We’ll use a finite state machine for controlMulticycle Approach3•Finite state machines:–a set of states and –next state function (determined by current state and the input)–output function (determined by current state and possibly input)–We’ll use a Moore machine (output based only on current state)Review: finite state machinesNext-statefunctionCurrent stateClockOutputfunctionNextstateOutputsInputs4Review: finite state machines•Example: B. 21 A friend would like you to build an “electronic eye” for use as a fake security device. The device consists of three lights lined up in a row, controlled by the outputs Left, Middle, and Right, which, if asserted, indicate that a light should be on. Only one light is on at a time, and the light “moves” from left to right and then from right to left, thus scaring away thieves who believe that the device is monitoring their activity. Draw the graphical representation for the finite state machine used to specify the electronic eye. Note that the rate of the eye’s movement will be controlled by the clock speed (which should not be too great) and that there are essentially no inputs.5•Break up the instructions into steps, each step takes a cycle–balance the amount of work to be done–restrict each cycle to use only one major functional unit•At the end of a cycle–store values for use in later cycles (easiest thing to do)–introduce additional “internal” registersMulticycle ApproachShiftleft 2PCMemoryMemDataWritedataMux01RegistersWriteregisterWritedataReaddata 1Readdata 2Readregister 1Readregister 2Mux01Mux014Instruction[15– 0]Signextend3216Instruction[25– 21]Instruction[20– 16]Instruction[15– 0]Instructionregister1Mux032MuxALUresultALUZeroMemorydataregisterInstruction[15– 11]ABALUOut01Address6Multicycle Datapath with control signalsS h iftle ft 2M e m to R e gIo rD M e m R e ad M e m W r iteP CM e m o ryM e m D a taW r ited a t aMux01R e g is t e rsW riter e g is te rW rited a t aR e a dd a t a 1R e a dd a ta 2R e a dr e g is te r 1R e a dr e g is te r 2In str u ct io n[1 5– 1 1]Mux01Mux014A L U O pA L U S r c BR eg D s t R eg W r iteIn str u ctio n[1 5 – 0 ]In str u c tio n [5 – 0 ]S ig ne x te n d3216In s t r u ctio n[2 5 – 2 1 ]In s t r u ctio n[2 0 – 1 6 ]In s t r u ctio n[1 5 – 0 ]In s tru ctio nre g is te r1Mux032A L Uc o ntro lMux01A L Ur e s u ltA L UA L US rc AZ e roABA L U O utIR W rit eA d d r e s sM e m o ryd a tar e g is te r7Multicycle Datapath & ControlShiftleft 2PCMux01RegistersWriteregisterWritedataReaddata 1Readdata 2Readregister 1Readregister 2Instruction[15– 11]Mux01Mux014Instruction[15– 0]Signextend3216Instruction[25– 21]Instruction[20– 16]Instruction[15– 0]InstructionregisterALUcontrolALUresultALUZeroMemorydataregisterABIorDMemReadMemWriteMemtoRegPCWriteCondPCWriteIRWriteALUOpALUSrcBALUSrcARegDstPCSourceRegWriteControlOutputsOp[5– 0]Instruction[31-26]Instruction [5–0]Mux02Jumpaddress [31-0]Instruction [25–0]26 28Shiftleft 2PC [31-28]11Mux032Mux01ALUOutMemoryMemDataWritedataAddress8•Instruction Fetch•Instruction Decode and Register Fetch•Execution, Memory Address Computation, or Branch Completion•Memory Access or R-type instruction completion•Write-back stepINSTRUCTIONS TAKE FROM 3 - 5 CYCLES!Five Execution Steps9High level view of finite state machine controlMemory accessinstructionsi r .R-type instructions( i . )Branch instruction(Figure . 0)Jump instruction( i r .Instruction fetch/decode and register fetch(Figure 5.37)Start10•Use PC to get instruction and put it in the Instruction Register.•Increment the PC by 4 and put the result back in the PC.•Can be described succinctly using RTL "Register-Transfer Language"IR = Memory[PC];PC = PC + 4;Can we figure out the values of the control signals?What is the advantage of updating the PC now?Step 1: Instruction Fetch11•Read registers rs and rt in case we need them•Compute the branch address in case the instruction is a branch•RTL:A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC + (sign-extend(IR[15-0]) << 2);•We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)Step 2: Instruction Decode and Register Fetch12Instruction Fetch & DecodeALUSrcA = 0ALUSrcB = 11ALUOp = 00MemReadALUSrcA = 0IorD = 0IRWriteALUSrcB = 01ALUOp = 00PCWritePCSource = 00Instruction fetchInstruction decode/Register fetch (Op = 'LW') or (Op = 'SW')(Op = R-type)(Op = 'BEQ')(Op = 'JMP')01StartMemory reference FSM(Figure 5.33)R-type FSM(Figure 5.34)Branch FSM(Figure 5.35)Jump FSM(Figure 5. 36)13•ALU is performing one of three functions, based on instruction type•Memory Reference:ALUOut = A + sign-extend(IR[15-0]);•R-type:ALUOut = A op B;•Branch:if (A==B) PC = ALUOut;Step 3 (instruction dependent)14•Loads and stores access


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WM CSCI 424 - multicycle

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