ACS Unit of Viterbi DecoderAgendaAbstractIntroductionProject DetailsArchitecture of ACS UnitLongest Path CalculationsSchematicLayoutVerificationSimulationsCost AnalysisLessons LearnedSummaryAcknowledgements1ACS Unit of Viterbi DecoderAudy ,Garrick Ng, Ichang Wu, Wen-Jiun YongAdvisor: Dave ParentSpring 20052Agenda•Abstract•Introduction•Project Details•Results•Cost Analysis•Conclusions3Abstract•8-bit ACS unit of Viterbi Decoder•Clock speed: 90 MHz•Average Power: mW•Average Power Density: W/cm2•Area: m x m4Introduction•commonly used in decoding convolutional codes in baseband detection for wireless communication and detection of recorded data in magnetic disk drives.•Consist of 3 sections:–BM (branch metric Unit)–ACS (add-compare-select Unit)–Survival Path Unit•ACS unit –consumes most power and area, also determine the speed of VB5Project Details•8-bit inputs ACS operates at 11ns (90MHz).•The project was divided into 8 bits CLA adders, 8 bits subtractor, 2:1 multiplexer and a register. •Output of the ACS specifics the minimum metric path of the two inputs ( A & B)6Architecture of ACS Unit7Longest Path Calculations8Schematic9Layout10Verification11Simulations12Cost Analysis•Estimated time spent on each phase of the project:–Architecture of the design (3 weeks)–verifying logic (1 week)–verifying timing (1 week)–layout (3 weeks)–post extracted timing (1 weeks)13Lessons Learned•Use Cell based design–Great for debugging & passing LVS–Save time in for multiple bits•Define a manageable scope of project –To meet project dateline14Summary•We designed an 8-bit ACS unit that operated at 90 MHz and uses mW of Power and occupied an area of m x m that can be used in Viterbi decoder• Future designs can definitely minimize area and power.15Acknowledgements•Thanks to our family for putting up with us.•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Synopsys for Software donation•Thanks to Professors Parents for his time & guidanceDo not read this slide, just show
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