6-Bit Serial MultiplierIntroductionSpecificationsPowerPoint Presentation1-bit schematicSchematicLongest Path CalculationsD Flip-Flop schematicD Flip-Flop transient responseFull Adder schematicFull adder verilog waveformFull Adder transient responseVerilog Waveform6bit serial multiplier simulationPower ConsumptionDRC & ExtractionLVSComplete Design LayoutTest resultsSummaryAcknowledgements6-Bit Serial MultiplierThu NguyenKenny YipChao-Ton YangMing LiAdvisor: Prof. David ParentDec 6, 2004Introduction•We design a 6-bit serial.•The advantage of this design over the parallel circuit is the reducing of required hardware and input, output routing when the high clock rate is not important factor in application.Specifications•Clock f = 100 MHz, duty cycle = 50%•Output Cload = 10 pF•Power < 500 mW•Tpavg < 5ns•Area < 600 mil2Block Diagram1-bit schematicSchematicLongest Path CalculationsLogic Level GateCg to Drive NSN NSP N M WN WPCg of Gate Tpavg1 DFF-NAND2 Slave 10 2 1 1 2 4 3.5 12.8 0.3122 DFF-Driver mux Slave 12.8 2 2 1 3 4.1 7 18.9 0.43 DFF-NAND2 Master 18.9 2 1 1 2 3.8 3.3 12.2 0.3124 DFF-Driver mux Master 12.2 2 2 2 2 3.2 5.4 14.7 0.45 MUX-INV 14.7 1 1 1 1 1.5 2.6 5.1 0.3126 MUX-NAND2 5.1 1 1 3 2 1.5 2.6 5 0.3127 FA-INV 5 1 1 1 1 1.5 2.6 5 0.3128 FA-AOI1 5 2 2 10 10 3.5 6.1 16.3 0.3129 FA-AOI2 16.3 2 2 7 7 3.5 5.8 15.8 0.31210 AND2-INV 15.8 1 1 1 1 1.5 2.6 5.4 0.31211 AND2-NAND2 5.4 2 1 1 2 2 1.76 4.8 0.31212 DFF-NAND2 Slave 4.8 2 1 1 2 1.7 1.5 5.4 0.31213 DFF-Driver mux Slave 5.4 2 2 1 3 3.9 6.8 18.3 0.35514 DFF-NAND2 Master 18.3 2 1 1 2 3.7 3.2 11.8 0.31215 DFF-Driver mux Master 11.8 2 2 2 2 3.1 5.3 14.4 0.4 Total Tpavg = 4.987* Note: All widths are in microns, capacitances in fF and time in nSD Flip-Flop schematicD Flip-Flop transient responseFull Adder schematicFull adder verilog waveformFull Adder transient responseVerilog Waveform6bit serial multiplier simulationTpavg = 4.2 nsPower Consumption•Pavg=1/2 x CL x f x VDD2 •P avg = 1/2 x 10 x 10-12 F x 100 x 106 Hz x 52 = 12.5mW for 1 component.•Power transient response of entire circuitry read from the simulation P = 148mW.DRC & ExtractionLVSComplete Design LayoutTest results•Tpavg = 4.2ns (< 5ns)•Total area A = 345 x 310m (1070 mil2 > 600 mil2)•Power P = 148mW (< 500 mW)Summary•Product test results meet most of specifications except the layout area are larger than 600 mil2 target specifications but we could easily reduced it if we have more time to rearrange all the compoments and routing. So Layout area is not actually a problem.•This a very challenge project, although we were not having much time left for project after the other heavy class works, this is the best we can accomplish.Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab•Thanks to Professor D. Parent•Thanks to our EE166
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