G22.2233 L04 Basic MIPS Architecture. 1 Banikazemi, NYU, 2007CS G22.2233 Computer Systems Design Spring 2007Lecture 04: Basic MIPS ArchitectureMohammad Banikazemi[Slides from Prof. Mary Jane Irwin, PSU Adapted fromComputer Organization and Design, Patterson & Hennessy, © 2005, UCB]G22.2233 L04 Basic MIPS Architecture. 2 Banikazemi, NYU, 2007Review: THE Performance Equation Our basic performance equation is thenCPU time = Instruction_count x CPI x clock_cycleInstruction_count x CPIclock_rateCPU time = -----------------------------------------------or These equations separate the three key factors that affect performanceO Can measure the CPU execution time by running the programO The clock rate is usually given in the documentationO Can measure instruction count by using profilers/simulators without knowing all of the implementation detailsO CPI varies by instruction type and ISA implementation for which we must know the implementation detailsG22.2233 L04 Basic MIPS Architecture. 3 Banikazemi, NYU, 2007 Our implementation of the MIPS is simplifiedO memory-reference instructions: lw, swO arithmetic-logical instructions: add, sub, and, or, sltO control flow instructions: beq, j Generic implementationO use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC)O decode the instruction (and read registers)O execute the instruction All instructions (except j) use the ALU after reading the registersHow? memory-reference? arithmetic? control flow?The Processor: Datapath & ControlFetchPC = PC+4DecodeExecG22.2233 L04 Basic MIPS Architecture. 4 Banikazemi, NYU, 2007Fetching Instructions Fetching instructions involvesO reading the instruction from the Instruction MemoryO updating the PC to hold the address of the next instructionReadAddressInstructionInstructionMemoryAddPC4O PC is updated every cycle, so it does not need an explicit write control signalO Instruction Memory is read every cycle, so it doesn’t need an explicit read control signalG22.2233 L04 Basic MIPS Architecture. 5 Banikazemi, NYU, 2007Decoding Instructions Decoding instructions involvesO sending the fetched instruction’s opcode and function field bits to the control unitInstructionWrite DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 2ControlUnitO reading two values from the Register File- Register File addresses are contained in the instructionG22.2233 L04 Basic MIPS Architecture. 6 Banikazemi, NYU, 2007Executing R Format Operations R format operations (add, sub, slt, and, or)O perform the (op and funct) operation on values in rs and rtO store the result back into the Register File (into location rd)InstructionWrite DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 2ALUoverflowzeroALU controlRegWriteR-type:31 25 20 15 5 0op rs rt rd functshamt10O The Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register FileG22.2233 L04 Basic MIPS Architecture. 7 Banikazemi, NYU, 2007Executing Load and Store Operations Load and store operations involvesO compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instructionO store value (read from the Register File during decode) written to the Data MemoryO load value, read from the Data Memory, written to the Register FileInstructionWrite DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 2ALUoverflowzeroALU controlRegWriteDataMemoryAddressWrite DataRead DataSignExtendMemWriteMemRead16 32G22.2233 L04 Basic MIPS Architecture. 8 Banikazemi, NYU, 2007Executing Branch Operations Branch operations involvesO compare the operands read from the Register File during decode for equality (zero ALU output)O compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instrInstructionWrite DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 2ALUzeroALU controlSignExtend16 32Shiftleft 2Add4AddPCBranchtargetaddress(to branch control logic)G22.2233 L04 Basic MIPS Architecture. 9 Banikazemi, NYU, 2007Executing Jump Operations Jump operation involvesO replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bitsReadAddressInstructionInstructionMemoryAddPC4Shiftleft 2Jumpaddress26428G22.2233 L04 Basic MIPS Architecture. 10 Banikazemi, NYU, 2007Creating a Single Datapath from the Parts Assemble the datapath segments and add control lines and multiplexors as needed Single cycle design – fetch, decode and execute each instructions in one clock cycleO no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders)O multiplexors needed at the input of shared elements with control lines to do the selectionO write signals to control writing to the Register File and Data Memory Cycle time is determined by length of the longest pathG22.2233 L04 Basic MIPS Architecture. 11 Banikazemi, NYU, 2007Fetch, R, and Memory Access PortionsMemtoRegReadAddressInstructionInstructionMemoryAddPC4Write DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 2ALUovfzeroALU controlRegWriteDataMemoryAddressWrite DataRead DataMemWriteMemReadSignExtend16 32ALUSrcG22.2233 L04 Basic MIPS Architecture. 12 Banikazemi, NYU, 2007Adding the Control Selecting the operations to perform (ALU, Register File and Memory read/write) Controlling the flow of data (multiplexor inputs)I-Type:op rs rtaddress offset31 25 20 15 0R-type:31 25 20 15 5 0op rs rt rd functshamt10ObservationsO op field alwaysin bits 31-26O addr of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is the base registerO addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructionsO offset for beq, lw, and sw always in bits 15-0J-type:31 25 0op target addressG22.2233 L04 Basic MIPS Architecture. 13 Banikazemi, NYU, 2007Single Cycle Datapath with Control UnitReadAddressInstr[31-0]InstructionMemoryAddPC4Write DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 2ALUovfzeroRegWriteDataMemoryAddressWrite DataRead