11Elec 326 Flip-FlopsFlip-FlopsObjectivesThis section is the first dealing with sequential circuits. It introduces Flip-Flops, an important building block for most sequential circuits. First it defines the most basic sequential building block, the RS latch, and investigates some of its properties. Then, it introduces clocks and shows how they can be used to synchronize latches to get gated latches. Finally, it extends gated latches to flip-flops by developing a more stable clocking technique called dynamic clocks. The Section also develops the state table behavioral model for gated latches and flip-flopsReading Assignment Chapter 3, Sections 3.1-3.3. 2Elec 326 Flip-FlopsLatches Problem: Design a network to control a lamp from two pushbutton switches labeled S and R. If we push switch S the light should turn on. If we then release S, the light should stay on. If we push switch R, the lamp should turn off and stay off after releasing R. Assume that both S and R are not pushed at the same time.+Lamp?RSQ+RSQ01 01 0 023Elec 326 Flip-Flops A Solution Construct a truth table for this circuit. Write Boolean expressions for X and Q.RSQXRS X Q000110110110X = (S+Q)'; Q = (R+X)'Q = R'•X' = R'•(S+Q) Let S = R = 0. Then Q = 1•(0+Q) = Q00Q’ X’4Elec 326 Flip-Flops The previous circuit is called an SR Latch and is usually drawn as shown below: Observations The latch has two states, Q = 0 and Q = 1 The output depends on the state as well as the inputs, so the circuit is sequential The circuit has a loop, as all sequential circuits do The outputs Q and Q_L are logical complements unless inputs S and R are both 1 Asserting S (i.e., setting it to 1) sets Q to 1 (and Q_L to 0). Asserting R (i.e., setting it to 1) resets Q to 0 ( and Q_L to 1) If neither S nor R are asserted, Q retains a value determined by the last time S or R were asserted Bad things can happen if both S and R are asserted simultaneously as we will see below.QQ_LRQQSLogic Diagram SymbolRS35Elec 326 Flip-FlopsUnstable latch behavior (Oscillation) Assume that all gates have a fixed delay δ modeled as follows: This gives the following latch model: Then Q(t+δ) = (R(t) + X(t))' = R(t)' • X(t)', and X(t+δ) = (S(t) + Q(t))' = S(t)' • Q(t)'δXYXYδY(t+δ) = X(t)δQ(t+δ)δX(t+δ)Q(t)X(t)RS6Elec 326 Flip-Flops Now set S = R = 1, so that both Q and X are equal to 0 after at most a delay of δ. Then change both R and S to 0 at exactly the same time. Then Q(t+δ) = X(t)' and X(t+δ) = Q(t)'δRSQXδδδ47Elec 326 Flip-FlopsUnstable latch behavior (Metastable state) Equivalent circuit for the latch when R = S = 0 Transfer characteristics of an inverter:vi1vo1vi2vo2voutvin8Elec 326 Flip-Flops Now consider the behavior of the following circuit: Superimposing the two graphs gives the following:Inverter 1Inverter 2vi1,vo2vo1, vi2vi1vo1vi2vo259Elec 326 Flip-Flops Now consider connecting v02to vi1The dots on the graph represent points where the inputs and outputs of the delays are equal. The dots on the two ends represent the two stable states of the system. Small changes in any of the signals are damped out quickly.The dot in the middle represents a metastable state. Small changes in any of the signals are amplified and the circuit leaves the metastable state. The hill analogy: The latch could get in the metastable state in the following way:What is the relationship between hazards and the metastable state?vo1 = vi2δ δvo2 = vi1RSQ10Elec 326 Flip-FlopsAvoiding unstable behavior of SR latches Since both the oscillation and the metastable state are undesirable behavior, we should try to avoid them. this can be done with the following rules:Do not change R and S from 1 to 0 at the same time. z This is necessary to avoid the oscillation behavior seen abovez One way to guarantee that this will not happen is to never allow them to both be 1 at the same time.Once you change an input, do not change it again until the circuit has had time to complete all its signal transitions and reach a stable state.z This is necessary to avoid the metastable behavior illustrated above611Elec 326 Flip-Flops/R/S Latch Changing from 00 to 11 can produce nondeterministic behaviorPropagation Delay of Ungated LatchestPRQ- Delay from the R input to the Q outputtPSQ- Delay from the S input to the Q outputtPRQ_L- Delay from the R input to the Q_L outputtPSQ_L- Delay from the S input to the Q_L outputSQtPSQR_LS_LQ_LQRQQSSymbolLogic Diagram12Elec 326 Flip-FlopsVerilog descriptions of an SR latchmodule srlatch1 (s, r, q, q_n);input s, r;output q, q_n;assign q_n = ~(s | q);assign q = ~(r | q_n);endmodulemodule srlatch2 (s, r, q);input s, r;output q;reg q; always @(s or r)if (s & r) q = 0;else if (~s & r) q = 0;else if (s & ~r) q = 1;endmodulemodule srlatch3 (s, r, q);input s, r;output q;reg q; always @(s or r)case ({s,r})3: q = 0;2: q = 1;1: q = 0;endcaseendmodule713Elec 326 Flip-FlopsGated LatchesClock Signals It is easier to avoid the metastable state if we place restrictions on when a latch can change states. This is usually done with a clock signal. The effect of the clock is to define discrete time intervals. The clock signal is used so that the latch inputs are ignored except when the clock signal is asserted. This effectively makes time discrete, since we do not care what happens when the clock is not asserted. 112 3 42345CK14Elec 326 Flip-FlopsGated SR Latch Gated Latch Function TableNote that when CK is 0, the simple latch has both inputs 0 and the inputs S and R have no effect RSQ_LQRQQSSymbolLogic DiagramCKCK000011110011001101010101Q(t)Q(t)Q(t)Q(t)Q(t)010SRCK Q(t+δ)815Elec 326 Flip-Flops Gated Latch Transition Table Note that the internal latch inputs will both go from 1 to 0 if the S and R inputs are both 1 when the clock goes low. Hence we must never have S and R at 1 when the clock is 1. We make the following rules for changing inputs.z Don't change the inputs while the clock is asserted.z Don't apply the inputs S = R = 1 when the clock is asserted. Then we can use the following model of latch behavior:z While the clock is not asserted, the inputs are ignored and the state does not change.z When the clock is asserted, the latch can change state and the values of the input signals S(t) and R(t) and current state Q(t) just prior to the clock assertion determine the new value
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