Comparators, FETs, Logic 02/19/2008 Lecture 10 1 Winter 2012 UCSD: Physics 121; 2012 2 Winter 2012 UCSD: Physics 121; 2012 3 + - Vref Vin Vout +5 V R 5 V Vref Vout Vin time V Winter 2012 UCSD: Physics 121; 2012 4 +5 V external circuit/loadComparators, FETs, Logic 02/19/2008 Lecture 10 2 Winter 2012 UCSD: Physics 121; 2012 5 5 V Vout Vin Winter 2012 UCSD: Physics 121; 2012 6 Winter 2012 UCSD: Physics 121; 2012 7 Winter 2012 UCSD: Physics 121; 2012 8 2N7000 FETComparators, FETs, Logic 02/19/2008 Lecture 10 3 Winter 2012 UCSD: Physics 121; 2012 9 FET BJT note pinout correspondence Winter 2012 UCSD: Physics 121; 2012 10 0 2 4 -2 -4 log current Vgate - Vsource p-channel MOSFET n-channel MOSFET n-channel JFET p-channel JFET Winter 2012 UCSD: Physics 121; 2012 11 source drain gate source gate drain 5 V 5 V 0 V 0 V 5 V 0 V + voltage + voltage 0 V 5 V < 5 V < 5 V n-channel MOSFET p-channel MOSFET “body” connection often tied to “source” Winter 2012 UCSD: Physics 121; 2012 12 A B C 0 0 0 0 1 0 1 0 0 1 1 1 AND A B C 0 0 0 0 1 1 1 0 1 1 1 1 OR A B C 0 0 0 0 1 1 1 0 1 1 1 0 XOR A B C 0 0 1 0 1 1 1 0 1 1 1 0 NAND A B C 0 0 1 0 1 0 1 0 0 1 1 0 NOR A B A B A B A B A B C bubbles mean inverted (e.g., NOT AND → NAND) A A C 0 1 1 0 NOTComparators, FETs, Logic 02/19/2008 Lecture 10 4 Winter 2012 UCSD: Physics 121; 2012 13 5 V 0 V input output 5 V 5 V 0 V 0 V 5 V 5 V 0 V 0 V A A C 0 1 1 0 NOT Winter 2012 UCSD: Physics 121; 2012 14 5 V 0 V IN A IN B OUT C A B C 0 0 1 0 1 1 1 0 1 1 1 0 NAND A B 0 V C Winter 2012 UCSD: Physics 121; 2012 15 5 V 0 V IN A IN B OUT C A B C 0 0 1 0 1 0 1 0 0 1 1 0 NOR 5 V A B C just a NAND flipped upside-down… Winter 2012 UCSD: Physics 121; 2012 16 A B C 0 0 1 0 1 1 1 0 1 1 1 0 NAND A B A C 0 1 1 0 NOT A B C 0 0 0 0 1 0 1 0 0 1 1 1 AND A B C 0 0 0 0 1 1 1 0 1 1 1 1 OR A B C 0 0 1 0 1 0 1 0 0 1 1 0 NOR invert output (invert NAND) invert both inputs invert inputs and output (invert OR)Comparators, FETs, Logic 02/19/2008 Lecture 10 5 Winter 2012 UCSD: Physics 121; 2012 17 A B C Winter 2012 UCSD: Physics 121; 2012 18 Winter 2012 UCSD: Physics 121; 2012 19 A B C 0 0 0 0 1 1 1 0 1 1 1 0 XOR A B Winter 2012 UCSD: Physics 121; 2012 20 Cin A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D Cout 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1Comparators, FETs, Logic 02/19/2008 Lecture 10 6 Winter 2012 UCSD: Physics 121; 2012 21 A B Cin D Cout F E H G A B Cin E F H G D Cout 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 Input Intermediate Output Each digit requires 6 gates Each gate has ~6 transistors ~36 transistors per digit + A B Cin D Cout “Integrated” Chip Winter 2012 UCSD: Physics 121; 2012 22 0 1 0 0 1 1 0 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 00101110 = 46 + 01001101 = 77 01111011 = 123 1 1 + + + + + + + + 0 MSB LSB = Least Significant Bit Carry-out tied to carry-in of next digit. “Magically” adds two binary numbers Up to ~300 transistors for this basic function. Also need –, ×, /, & lots more. Integrated one-digit binary arithmetic unit (prev. slide) Winter 2012 UCSD: Physics 121; 2012 23 Winter 2012 UCSD: Physics 121; 2012