Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41What You Need to Knowfor Project OneBruce MaggsDave EckhardtJoey EcheverriaSteve MuckleCarnegie Mellon University 1Synchronization1.Please read the syllabusa) Some of your questions are answered there :-)b) We would rather teach than tear our hair out2.Also the Project 1 handouta) Please don't post about “Unexpected interrupt 0”3.Reflections on Project 0...Carnegie Mellon University 1Overview1.Introduction2.Project One Motivation3.Mundane Details (x86/IA-32 version)PICs, hardware interrupts, software interrupts and exceptions, the IDT, privilege levels, segmentation4.Writing a Device Driver5.Installing and Using SimicsCarnegie Mellon University 1Project 1 Motivation1.What are our hopes for project 1?a) introduction to kernel programmingb) a better understanding of the x86 archc) hands-on experience with hardware interrupts and device driversd) get acquainted with the simulator (Simics) and development toolsCarnegie Mellon University 1Mundane Details in x861.Kernels work closely with hardware2.This means you need to know about hardware3.Some knowledge (registers, stack conventions) is assumed from 15-2134.You will learn more x86 details as the semester goes on5.Use the Intel PDF files as reference (http://www.cs.cmu.edu/~410/projects.html)Carnegie Mellon University 1Mundane Details in x86: Privilege Levels1. Processor has 4 “privilege levels” (PLs)2. Zero most privileged, three least privileged3. Processor executes at one of the four PLs at any given time4. PLs protect privileged data, cause general protection faultsCarnegie Mellon University 1Mundane Details in x86: Privilege Levels1. Essentially unused in Project 12. Projects 2 through 4a) PL0 is “kernel”b) PL3 is “user”c) Interrupts & exceptions usually transfer from 3 to 0d) Running user code means getting from 0 to 3Carnegie Mellon University 1Memory Segmentation 1. There are different kinds of memory2. Hardwarea) Read-only memory (for booting)b) Video memory (painted onto screen)c) ...3. Softwarea) Read-only memory (typically, program code)b) Stack (grows down), heap (grows up)c) ...Carnegie Mellon University 1Memory Segmentation 1. Memory segment is a range of “the same kind”2. Hardwarea) Mark video memory as “don't buffer writes”3. Softwarea) Mark all code pages read-only4. Fancy softwarea) Process uses many separate segmentsb) Windows: each DLL is a segmentCarnegie Mellon University 1Memory Segmentation 1. x86 hardware loves segments2. Mandatory segmentsa) Stackb) Codec) Data3. Segments interact with privilege levelsa) Kernel stack / user stackb) Kernel code / user codec) ...Carnegie Mellon University 1Mundane Details in x86:Segmentation 1. When fetching an instruction, the processor asks for an address that looks like this: %CS:%EIP2. So, if %EIP is 0xbabe then %CS:%EIP is the 47806th byte of the “code segment”.Carnegie Mellon University 1x86 Segmentation Road Map 1. Segment = range of “same kind of memory”2. Segment register = %CS, %SS, %DS, ... %GS3. Segment selector = contents of a segment registera) Which segment do we mean (table, index)?b) What access privilege do we have to it?4. Segment descriptor = definition of segmenta) Which memory range?b) What are its propertiesCarnegie Mellon University 1Mundane Details in x86:Segmentation 1. When fetching an instruction, the processor asks for an address that looks like this: %CS:%EIP2. The CPU looks at the segment selector in %CS3. A segment selector looks like this:Carnegie Mellon University 1Mundane Details in x86:Segmentation 1. Segment selector has a segment number, table selector, and requested privilege level (RPL)2. The table-select flag selects a descriptor tablea) global descriptor table or local descriptor table3. Segment number indexes into that descriptor tablea) 15-410 uses only global descriptor table (whew!)4. Descriptor tables set up by operating systema) 15-410 support code makes GDT for you (whew!)5. You will still need to understand this, though...Carnegie Mellon University 1Mundane Details in x86:Segmentation 1. Segment selector has a segment number, table selector, and requested privilege level (RPL)2. Table selector (done)3. Segment number/index (done)4. RPL generally means “what access do I have?”5. Magic special case: RPL in %CSa) Defines current processor privilege levelb) Think: “user mode” vs. “kernel mode”c) Remember this for Project 3!!!Carnegie Mellon University 1Mundane Details in x86:Segmentation 1. Segments = area of memory with particular access/usage constraints2. Base, size, “stuff”3. Layout:Carnegie Mellon University 1Mundane Details in x86:Segmentation 1. Consider %CS segment register's segment selector's segment descriptor2. Assume base = 0xcafe00003. Assume limit > 478064. Then %CS:%EIP means “linear virtual address” 0xcafebabe5. “Linear virtual address” fed to virtual memory system (Project 3)Carnegie Mellon University 1Implied Segment Registers 1. Programmer doesn't usually specify segment2. Usually implied by “kind of memory access”3. CS is the segment register for fetching code4. SS is the segment register for the stack segmenta) Implied by PUSH and POP family5. DS is the default segment register for data accessa) But ES, FS, and GS can also be usedCarnegie Mellon University 1Mundane Details in x86:Segmentation1.Segments need not be backed by physical memory and can overlap2.Segments defined for 15-410:Kernel Code Kernel Data User Code User Data0xFFFFFFFF0x00000000Not This ProjectCarnegie Mellon University 1Mundane Details in x86:Segmentation1.Why so many?2.You can’t specify a segment that is readable, writable and executable.3.Therefore one for readable/executable code4.Another for readable/writable data5.Need user and kernel segments in Project 3 for protection6.(Code, Data) X (User, Kernel)Carnegie Mellon University 1Mundane Details in x86:Segmentation1.Don’t need to be concerned with every detail of segments in this class2.For more information you can read the Intel docs3.Or our documentation at: 4. http://www.cs.cmu.edu/~410/doc/segments/segments.htmlCarnegie Mellon University 1Mundane Details in x86: Getting into Kernel Mode1.How do we get