04/26/05 Instruction encoding 1Instruction encoding•We’ve already seen some important aspects of processor design.–A datapath contains an ALU, registers and memory.–Programmers and compilers use instruction sets to issuecommands.•Now let’s complete our processor with a control unit that convertsassembly language instructions into datapath signals.–Today we’ll see how control units fit into the big picture, andhow assembly instructions can be represented in a binary format.–On Wednesday we’ll show all of the implementation details forour sample datapath and assembly language.04/26/05 Instruction encoding 2•We can use branch instructions to translate high-level conditionalstatements into assembly code.•Sometimes it’s easier to invert the original condition. Here, weeffectively changed the R1 < 0 test into R1 >= 0.Transl ating the C if-then statementR1 = *X;if (R1 < 0)R1 = -R1;R3 = R1 + R1;LD R1, (X) // R1 = *XBNN R1, L // Skip MUL if R1 is not negativeLD R2,#0SUB R1, R2, R1 // R1 = 0-R1L ADD R3, R1, R1 // R3 = R1 + R104/26/05 Instruction encoding 3Translating the C for loop•Here is a translation of the for loop, using a hypothetical BGT branch.LD R1, #0 // R1 = 0LD R2, #1 // R2 = 1FOR BGT R2, #5, L // Stop when R2 > 5ADD R1, R1, R2 // R1 = R1 + R2ADD R2, R2, #1 // R2++JMP FOR // Go back to the loop testL ADD R3, R1, R1 // R3 = R1 + R1R1 = 0;for (R2 = 1; R2 <= 5; R2++)R1 = R1 + R2;R3 = R1 + R1;04/26/05 Instruction encoding 4Summary of ISA•Machine language is the interface between software and processors.•High-level programs must be translated into machine languagebefore they can be run.•There are three main categories of instructions.–Data manipulation operations, such as a dding or s hifting–Data transfer operations to copy data between registers and RAM–Control fl ow instructions to change the execution order•Instruction set architectures depend highly on the host CPU’s design.–Today we saw instructions th at would be appropriate for ourdatapath from last week.–On Wednesday we’ll look at some other possibilities.04/26/05 Instruction encoding 5Review: Datapath•Recall that our ALU hasdirect access only to theregister file.•RAM contents must becopied to the registersbefore they can be used asALU operands.•Similarly, ALU results mustgo through the registersbefore they can be storedinto memory.•We rely on data movem entinstructions to transfer databetween the RAM and theregister file.D dataWriteD addressA address B addressA data B dataRegister FileWRDAAA BAQ D1D0SRAMADRSDATACSWROUTMW+5VA BALUFZNCVFSFSMDS D1 D0QConstantMB04/26/05 Instruction encoding 6Block diagram of a processor•The control unit connects programs with the datapath.–It converts program instructions into control words for thedatapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.–It executes program i nstructions in the correct sequence.–It generates the “constant” input for the datapath.•The datapath also sends information back to the control unit. Forinstance, the ALU status bits V, C, N, Z can be inspected by branchinstructions to alter a program’s control flow.ControlUnitDatapathControl signalsStatus signalsProgram04/26/05 Instruction encoding 7A specific instruction set•The first thing we must do is agree upon an instruction set.•For our example CPU let’s stick with the three-address, register-to-register instruction set architecture introduced i n th e las t lectur e.–Data manipulation instructions have on e destination and up totwo sources, which must be either registers or constants.–We include dedicated load and store instructions to transfer datato and from memory.•Next week, we’ll learn about different kinds of instruction sets.04/26/05 Instruction encoding 8From assembly to machine language•Next, we must define a machine language, or a binary representationof the assembly instructions that our processor supports.•Our CPU includes three types of instructions, which have differentoperands and will need different representations.–Register format instructions require two sou rce registers.–Immediate format instructions have one source re gister and oneconstant operand.–Jump and branch format instructions nee d one source registerand one constant address.•Even though there are three different instruction formats, it is be stto make their binary representations as similar as possible.–This will make the control unit hardware simpler.–We’ll start by making all of our instructions 16 bits long.04/26/05 Instruction encoding 9Register format•An example register-format instruction:ADD R1, R2, R3•Our binary representation for these instructions will include:–A 7-bit opcode field, specifying the operation (e.g., ADD).–A 3-bit destination register, DR.–Two 3-bit source registers, SA a nd SB.OpcodeDestinationRegister(DR)S ourceRegister A(S A)S ourceRegister B(S B)15 9 8 6 5 3 2 004/26/05 Instruction encoding 10Immediate format•An example immediate-format instruction:ADD R1, R2, #3•Immediate-format instructions will consist of:–A 7-bit instruction opcode.–A 3-bit destination register, DR.–A 3-bit source register, SA.–A 3-bit constant operand, OP.OpcodeDestinationRegister(DR)S ourceRegister A(S A)Operand(OP)15 9 8 6 5 3 2 004/26/05 Instruction encoding 11•We will use PC-re lative addressing for jumps and branches, w herethe operand specifies the number of addresses to jump or branchfrom the current instruction.•We can assume each instruction occupies one word of memory.•The operand is a signed number.–It’s possible to jump or branch either “forwards” or “backwards.”–Backward jumps are often used to implement loops; see some ofthe examples from last week.LD R1, #10 1000 LD R1, #10LD R2, #3 1001 LD R2, #3JMP L 1002 JMP 2K LD R1, #20 1003 LD R1, #20LD R2, #4 1004 LD R2, #4L ADD R3, R3, R2 1005 ADD R3, R3, R2ST (R1), R3 1006 ST (R1), R3PC-relative jumps and branches04/26/05 Instruction encoding 12Jump and branch format•Two example jump and branch instructions:BZ R3, -24JMP 18•Jump and branch format instructions include:–A 7-bit instruction opcode.–A 3-bit source register SA for branch cond itions.–A 6-bit address field, AD, for storing jump or branch offs ets.•Our branch instructions support only one source register. Othertypes of branches can be simulated from these basic ones.OpcodeAddressBits 5-3(AD)S ourc eRegister A(S A)AddressBits 2-0(AD)15 9 8 6 5 3 2