Chemical Vapor DepositionLithographyDirect Step on Wafer (DSW) AlignerComparison of Step and Repeat vs. Step and ScanLithography: Alignment and ExposureCharacteristics of Negative and Positive ResistsPhotoresist DevelopEtch (material removal)Applied Materials 5000 Etch Process ChamberThe PlasmaEtch ChemistriesEtchPhotolithography Process Flow ChartCMP ProcessingIon ImplantPeriodic Table of the ElementsTypical Ion Implantation EquipmentFuture Trends1Chemical Vapor Deposition•Dielectrics:- Epitaxial growth. Single crystal. Batch to single wafer.- Silicon Dioxide (Oxide). Alternative to batch furnace.- SACVD Oxides: BPSG (PMD), FSG, USG (IMD), TEOS/03- Silicon Nitride• Conductors:- mainly Tungsten. High aspect ratio plugs.• Single wafer processing.2Lithography•The most critical process in IC manufacturing•Patter transfer process•Leading edge (sub-wavelength lithography):248nm light to pattern 130nm features- phase shifting masks/reticles- optical proximity correction•Next generation: 193nm, 57nm, 13nm3Direct Step on Wafer (DSW) AlignerOptical Configuration4Comparison of Step and Repeat vs. Step and ScanLithography tool types5Lithography: Alignment and Exposure(Stepper/Scanner)6Characteristics of Negative and Positive Resists7Photoresist DevelopPositive Resist8Etch (material removal)•Wet (chemical bath) for > 3 microns or Dry (plasma reactor) < 3 microns•Conductors (31%), polysilicon (25%), oxide etch (44%)•Metal etch 35 - 40 wph.9Applied Materials 5000 Etch Process ChamberSource: Applied Materials (AMAT)10The PlasmaThe plasma supplies etchants which must remove the film selectively; Ideally the mask and substrate are not attacked.Source: D.L. Flamm, 199611Etch ChemistriesSource: D.L. Flamm, 199612EtchMetal Etch typically dry (Plasma Reactor) etch* Al to resist etch selectivity: 3:113Photolithography Process Flow Chart14CMP ProcessingOxide and CopperCMP (oxide)- used with AL todayCMP (for Copper)Why CMP for copper?- because no-one canfigure out how to etchcopper at low temperature.1. Deposit blanket metalAL DEPSLSLAL ALAL2. Litho (expose and develop) and etchSL3. Oxide Deposition (CVD)OxideSLAL ALAL4. CMP (grind down, flat)OXOxideAL ALAL1. Deposit blanket oxideOxideSLSLOX OXOX2. Litho and etch oxideSL3. Blanket Copper DepositionCUSLOX OXOX4. CMP (grind down and flatten)CU CUOX OXOX3 Steps for Deposition1. CU barrier(Ta, TaN) using PVD2. CU seed using PVD3. CU bulk using ECD15Ion Implant•Doping process (changes the electrical characteristics of the material)•Creates the elements of the transistors•Fires ions of dopant material into the wafer•P (positive) dopants OR N (negative) dopants•Older doping process: diffusion•Need to repair damages from bombardment: anneal or Rapid Thermal Processing (RTP)16Periodic Table of the Elements17Typical Ion Implantation EquipmentSource: SJSUSection CFuture Trends19Future Trends•300 nm wafer processing. Ramp occurring slowly.•New materials:- Cu is here. High-end Logic (3.06GHz P4). - low-k dielectrics. Next major material change. - dielectric substrate engineering: SOI, Strained Silicon.- high-k dielectric materials for gates •Economics may limit Moore’s Law, not physics !The information contained herein is based on sources Adams, Harkness & Hill believes to be reliable, but it is neither all-inclusive nor guaranteed to be accurate. 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