RIT EECC 361 - VHDL Synthesis of a MIPS­32 Processor

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VHDL Synthesis of a MIPS-32 ProcessorFinal ProjectInstructor: Dr. HsuCourse Number: 0306-731-01Submitted: 5/11/05Bryan Allen ([email protected])Dave Chandler([email protected])Nate Ransom([email protected])Directory of Sources:cpu.vhdcpu_tb.vhdinstr_fetch_stage.vhdinstr_fetch_stage_tb.vhdpc.vhdpc_test.vhdinstr_mem.vhdinstr_mem_tb.vhdinstr_mem_adder.vhdDecodeStage.vhdDecodeStageTestBench.vhdcontrol.vhdCNTRL_TEST.vhdreg_bank.vhdreg_bank_tb.vhdhazardDetection.vhdhazardDetectionTestBench.vhdsign_extend.vhdsign_extend_test.vhdExeStage.vhdExeStageTestBench.vhd1alu.vhdaluTestBench.vhddetermineBranch.vhddetermineBranchTestBench.vhdforwardingUnit.vhdforwardingUnitTestBench.vhdmem_stage.vhdmem_stage_test.vhdCover Page Continued:data_mem.vhddata_mem_tb.vhdwriteback.vhdwriteback_test.vhdConstraint Filesstandard_script.tclvirtual_clock_script.tcldw_compatible_script.tclfinal_cpu_script.tclFunctional blocks and designers:Instruction Fetch Stage: Nate Ransom/ Bryan AllenInstructionDecode Stage: Dave Chandler/ Nate RansomExecute Stage: Dave Chandler / Nate RansomMemory Stage: Nate Ransom/ Bryan AllenWrite Back Stage: Bryan Allen2Table of ContentsTable of Contents...................................................................................3Abstract.................................................................................................4Description of Theory and Algorithms...................................................4Functional description of different modules..........................................7Instruction Fetch Stage......................................................................7Instruction Fetch Test Bench..............................................................7Program Counter................................................................................8Program Counter Test Bench.............................................................8Instruction Memory............................................................................8Instruction Memory Test Bench.........................................................8Instruction Memory Address Adder...................................................8Decode Stage......................................................................................8Decode Stage Test Bench...................................................................9Control Unit........................................................................................9Control Unit Test Bench.....................................................................9Hazard Detection Unit........................................................................9Hazard Detection Unit Test Bench.....................................................9Sign Extender.....................................................................................9Register Bank.....................................................................................9Register Bank Test Bench.................................................................10Execute Stage...................................................................................10Execute Stage Test Bench................................................................10ALU...................................................................................................10ALU Test Bench................................................................................10Branch Determiner...........................................................................10Branch Determiner Test Bench........................................................11Forwarding Unit...............................................................................11Forwarding Unit test bench..............................................................11Memory Stage..................................................................................11Memory Stage Test Bench................................................................11Data_Mem.........................................................................................11Data_Mem Test Bench......................................................................11WriteBack Stage...............................................................................12Write Back Stage Test Bench...........................................................12Top Level..............................................................................................12Synthesis Results.................................................................................13Summary and Conclusion....................................................................14Division of Work...................................................................................15Simulation Waveforms With Sign off verificationAppendix A: Code Listing1Appendix B: TCL ScriptsAppendix C: CPU Reports3AbstractThe general purpose of this project is to implement a basic 5 stage pipelined MIPS32 cpu. Particular attention will be paid to the reduction of clock cycles for lower instruction latency as well as taking advantage of high-speed components in an attempt toreach a clock speed of at least 100 Mhz. The final results allowed the CPU to be run at over 200 Mhz with a very reasonable chip area of around 900,000 nm2.Description of Theory and AlgorithmsA MIPS-32 compatible Central Processing Unit (CPU) was designed, tested, and synthesized. The processor had the following attributes:· 5 stage pipeline · Hazard Detection and correction· Data Forwarding to reduce stall cyclesIn order to allow the simulation of the CPU program data files were created and read into the instruction memory of the CPU. A small amount of memory for both data and instructions was also included to prove the concept and functionality of the CPU while also maintaining focus on the optimization of control and data path units of the main CPUdesign.The processor designed was a traditional five stage pipeline design. The stages were Instruction Fetch, Instruction Decode, Execute, Memory Access, and Write Back. The Instruction Fetch stage is where a program counter will pull the next instruction fromthe correct location in program memory. In addition the program counter was updated with either the next instruction location sequentially, or the instruction location as determined by a branch. The Instruction Decode stage is where the control unit determines what values the controllines must be set to depending on the instruction. In addition,


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RIT EECC 361 - VHDL Synthesis of a MIPS­32 Processor

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