San Jose State University Department of Electrical Engineering December 11 Fall 2001OutlineIntroductionSPECIFICATIONDESIGN PRINCIPLEGate-level schematicParameters4bit serial to parallel converterMask LayoutSimulated I/O waveformsConclusionSan Jose State UniversitySan Jose State UniversityDepartment of Electrical EngineeringDepartment of Electrical EngineeringDecember 11 Fall 2001December 11 Fall 2001 EE 166 PROJECTEE 166 PROJECTProf. David ParentProf. David ParentGroup MembersGroup MembersKhanh Quan, Thy tran, Yan Wang ,Cecilia CheungKhanh Quan, Thy tran, Yan Wang ,Cecilia Cheung4BIT SERIAL TO PARALLEL CONVERTEROutlineOutline•Introduction•Specifications•Design Principle •Results •ConclusionIntroductionIntroductionFunctionality:Functionality:Input a serial data streamInput a serial data streamOutput a 4 bit parallel bit streamOutput a 4 bit parallel bit streamApplications:Applications:Serial to parallel converter Serial to parallel converterSPECIFICATIONSPECIFICATIONDesign challengesDesign challengesMinimize clock skewMinimize clock skewWorst case power used < 500 mWWorst case power used < 500 mWV switching TH=2.5 VV switching TH=2.5 VArea < 1800 um x 1800 umArea < 1800 um x 1800 umAble to drive a 10pF load at 10MhzAble to drive a 10pF load at 10MhzDESIGN PRINCIPLEDESIGN PRINCIPLEDesign block diagramDesign block diagramGate-level schematicGate-level schematicParametersParametersInverter: Wn=4um Wp=9.6umInverter: Wn=4um Wp=9.6umNand_2: Wn=4um Wp=4umNand_2: Wn=4um Wp=4umNand_3: Wn=8 Wp=4umNand_3: Wn=8 Wp=4umOutput Buffer:Output Buffer:11stst stage: Wn=4um Wp=9.6um stage: Wn=4um Wp=9.6um22ndnd stage: Wn=12.8um Wp=30.8um stage: Wn=12.8um Wp=30.8um33rdrd stage: Wn=46.6 Wp=99.6um stage: Wn=46.6 Wp=99.6um44thth stage: Wn=133.6um Wp=320.6um stage: Wn=133.6um Wp=320.6um4bit serial to parallel 4bit serial to parallel converterconverterMask LayoutMask LayoutSimulated I/O waveformsSimulated I/O waveformsConclusionConclusionAchievements:Achievements:Problems:Problems:Reasonable area Reasonable area Vth= 2.42VVth=
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