1BR 8/99 1DFFs are most common• Most programmable logic families only have DFFs• DFF is fastest, simplest (fewest transistors) of FFs• Other FF types (T, JK) can be built from DFFs• We will use DFFs almost exclusively in this class– Will always used edge-triggered state elements(FFs), not level sensitive elements (latches).BR 8/99 2Synchronous vs Asynchronous InputsSynchronous input: Output will change after active clock edgeAsychronous input: Output changes independent of clockDQCSRFlip-Flops often have async set, reset control.D input is synchronous with respect to ClkS, R are asynchronous. Q output affected by S,R independent of C. Async inputs are dominantover Clk. S,R inputs often called Pre (preset)and Clr (clear) inputs.BR 8/99 3DFF with async controlCD inputQ (FF)RS2BR 8/99 4Flip-Flop, Latch Timing• Propagation Delay– C2Q: Q will change some propagation delay afterchange in C. Value of Q is based on D input forDFF.– S2Q, R2Q: Q will change some propagation delayafter change on S input, R input– Note that there is NO propagation delay D2Q forDFF!– D is a Synchronous INPUT, no prop delay value forsynchronous inputsBR 8/99 5Clock to Q Propagation DelayCD inputQ (FF)Tc2qlhTc2qhlThere is NO delay from D to Q!!! The clock input is whattriggers the change, not the D input!!!BR 8/99 6S, R to Q Propagation DelayCD inputQ (FF)SRTs2qlhTr2qhl3BR 8/99 7Setup, Hold Times• Synchronous inputs (e.g. D) have Setup, Holdtime specification with respect to the CLOCKinput• Setup Time: the amount of time thesynchronous input (D) must be stable before theactive edge of clock• Hold Time: the amount of time thesynchronous input (D) must be stable after theactive edge of clock.BR 8/99 8Setup, Hold TimetsuthdCD changingStableIf changes on D input violate either setup or holdtime, then correct FF operation is not guaranteed.Setup/Hold measured around active clock edge.D
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