NYU CSCI-GA 2233 - Multiple Issue Introduction

Unformatted text preview:

G22.2233 L07 Multiple Issue Introduction. 1 Banikazemi, NYU, 2007CS G22.2233 Computer Systems Design Spring 2007Lecture 07: Multiple Issue IntroductionMohammad Banikazemi[Slides from Prof. Mary Jane Irwin, PSU Adapted fromComputer Organization and Design, Patterson & Hennessy, © 2005, UCB]G22.2233 L07 Multiple Issue Introduction. 2 Banikazemi, NYU, 2007Review: Pipeline Hazards Structural hazardsO Design pipeline to eliminate structural hazards Data hazards – read before writeO Use data forwarding inside the pipelineO For those cases that forwarding won’t solve (e.g., load-use) include hazard hardware to insert stalls in the instruction stream Control hazards – beq, bne,j,jr,jalO Stall – hurts performanceO Move decision point as early in the pipeline as possible – reduces number of stalls at the cost of additional hardwareO Delay decision (requires compiler support) – not feasible for deeper pipes requiring more than one delay slot to be filledO Predict – with even more hardware, can reduce the impact of control hazard stalls even further if the branch prediction (BHT) is correct and if the branched-to instruction is cached (BTB)G22.2233 L07 Multiple Issue Introduction. 3 Banikazemi, NYU, 2007Dealing with Exceptions Exceptions (aka interrupts) are just another form of control hazard. Exceptions arise fromO R-type arithmetic overflowO Trying to execute an undefined instructionO An I/O device requestO An OS service request (e.g., a page fault, TLB exception)O A hardware malfunction The pipeline has to stop executing the offending instruction in midstream, let all prior instructions complete, flush all following instructions, set a register to show the cause of the exception, save the address of the offending instruction, and then jump to a prearranged address (the address of the exception handler code) The software (OS) looks at the cause of the exception and “deals” with itG22.2233 L07 Multiple Issue Introduction. 4 Banikazemi, NYU, 2007Two Types of Exceptions Interrupts – asynchronous to program executionO caused by external events O may be handled between instructions, so can let the instructions currently active in the pipeline complete before passing control to the OS interrupt handlerO simply suspend and resume user program Traps (Exception) – synchronous to program executionO caused by internal eventsO condition must be remedied by the trap handler for thatinstruction, so much stop the offending instruction midstreamin the pipeline and pass control to the OS trap handlerO the offending instruction may be retried (or simulated by the OS) and the program may continue or it may be abortedG22.2233 L07 Multiple Issue Introduction. 5 Banikazemi, NYU, 2007Where in the Pipeline Exceptions Occur Arithmetic overflow Undefined instruction TLB or page fault I/O service request Hardware malfunctionALUIMRegDM RegStage(s)? Synchronous?G22.2233 L07 Multiple Issue Introduction. 6 Banikazemi, NYU, 2007Where in the Pipeline Exceptions Occur Arithmetic overflow Undefined instruction TLB or page fault I/O service request Hardware malfunctionALUIMRegDM RegStage(s)? Synchronous?EXIDIF, MEManyanyyesyesyesnono Beware that multiple exceptions can occur simultaneously in a single clock cycleG22.2233 L07 Multiple Issue Introduction. 7 Banikazemi, NYU, 2007Multiple Simultaneous ExceptionsInstr.OrderInst 0Inst 1Inst 2Inst 4Inst 3ALUIMRegDM RegALUIMRegDM RegALUIMRegDM RegALUIMRegDM RegALUIMRegDM Reg Hardware sorts the exceptions so that the earliest instruction is the one interrupted firstG22.2233 L07 Multiple Issue Introduction. 8 Banikazemi, NYU, 2007Multiple Simultaneous ExceptionsInstr.OrderInst 0Inst 1Inst 2Inst 4Inst 3ALUIMRegDM RegALUIMRegDM RegALUIMRegDM RegALUIMRegDM RegALUIMRegDM RegD$ page faultarithmetic overflowundefined instructionI$ page fault Hardware sorts the exceptions so that the earliest instruction is the one interrupted firstG22.2233 L07 Multiple Issue Introduction. 9 Banikazemi, NYU, 2007Additions to MIPS to Handle Exceptions (Fig 6.42) Cause register (records exceptions) – hardware to record the cause of the exceptions in Cause register and a signal to control writes to it (CauseWrite) EPC register (records the addresses of the offending instructions) – hardware to record in EPC the address of the offending instruction and a signal to control writes to it (EPCWrite)O Exception software must match exception to instruction A way to load the PC with the address of the exception handlerO Expand the PC input mux where the new input is hardwired to the exception handler address - (e.g., 8000 0180hexfor arithmetic overflow) A way to flush offending instruction and the ones that follow itG22.2233 L07 Multiple Issue Introduction. 10 Banikazemi, NYU, 2007Datapath with Controls for Exceptions (Incomplete)ReadAddressInstructionMemoryPC4Write DataRead Addr 1Read Addr 2Write AddrRegFileRead Data 1ReadData 21632ALUShiftleft 2AddDataMemoryAddressWrite DataRead DataIF/IDSignExtendID/EXEX/MEMMEM/WBControl01ALUcntrlBranchPCSrcForwardUnitHazardUnit010CompareForwardUnitAddIF.Flush08000 0180hexCauseEPCG22.2233 L07 Multiple Issue Introduction. 11 Banikazemi, NYU, 2007Summary All modern day processors use pipelining for performance (a CPI of 1 and fast a CC) Pipeline clock rate limited by slowest pipeline stage –so designing a balanced pipeline is important Must detect and resolve hazardsO Structural hazards – resolved by designing the pipeline correctlyO Data hazards- Stall (impacts CPI)- Forward (requires hardware support)O Control hazards – put the branch decision hardware in as early a stage in the pipeline as possible- Stall (impacts CPI)- Delay decision (requires compiler support)- Static and dynamic prediction (requires hardware support)G22.2233 L07 Multiple Issue Introduction. 12 Banikazemi, NYU, 2007Extracting Yet More Performance Two options:O Increase the depth of the pipeline to increase the clock rate –superpipelining (more details to come)O Fetch (and execute) more than one instructions at one time (expand every pipeline stage to accommodate multiple instructions) – multiple-issue Launching multiple instructions per stage allows the instruction execution rate, CPI, to be less than 1O So instead we use IPC: instructions per clock cycle- E.g., a 6 GHz, four-way multiple-issue processor can execute at a peak rate of 24 billion instructions per second with a best


View Full Document

NYU CSCI-GA 2233 - Multiple Issue Introduction

Download Multiple Issue Introduction
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Multiple Issue Introduction and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Multiple Issue Introduction 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?