Sensor System RequirementsPower Aware Microsensor ConsiderationsFirst Generation Wireless MicrosensorOS-Controlled Power Down ModesDynamic Voltage ScalingDistributed Processing Exploiting DVSEnergy Scalable AlgorithmsPower Aware RadioRF Start-up Energy OverheadIntegrated System-on-a-Chip VisionWhy Not Software?What about FPGAs?New Energy Metrics in DSM InterconnectOptimal VDD and VT ControlEnergy Efficiency of Digital ComputationAdaptive VDD/VT ArchitectureFast Startup TransmitterNew Opportunities: “Digital” UWB RadioMultihop and the Characteristic DistanceAnalogy to Buffered InterconnectDithering of Characteristic DistanceClustering ProtocolsAPI and Middleware LayerAPI-Controlled Operational PolicyEnergy ScavengingVibration-to-Electric EnergyProximity Sensor: Wireless Power SupplyHeel-Strike Energy Harvesting3D IntegrationPower Aware Wireless Microsensor Power Aware Wireless Microsensor SystemsSystemsAnantha Chandrakasan, Rex Min, Manish Bhardwaj, Seong-Hwan Cho, Alice WangMassachusetts Institute of TechnologyEmerging Microsensor ApplicationsEmerging Microsensor ApplicationsIndustrial Plants and Power Line Monitoring(courtesy ABB)Operating Room of the Future(courtesy John Guttag)NASA/JPL sensorwebsTarget Tracking & Detection(Courtesy of ARL)Location Awareness(Courtesy of Mark Smith, HP)WebsignSensor System RequirementsSensor System Requirements10 – 100mTransmission DistanceSmall SizeExtended LifetimeSpatial DensityData RateApplication Characteristics5 years1 “AA” battery0.1-10 nodes/m2bps to kbpsTypical ValuesPredictable ConstraintsPredictable ConstraintsUnpredictable DiversityUnpredictable Diversity Network roles:relay, sensor, aggregator Environment: event and signal statistics User/Application: required latency, qualityApplicationApplication--specific designs specific designs provide energy efficient point provide energy efficient point solutionssolutionsPowerPower--aware designs aware designs adapt energy adapt energy consumption to operating consumption to operating conditionsconditionsPower Aware Microsensor ConsiderationsPower Aware Microsensor ConsiderationsEnergy HarvestingAPI and ControlRF InnovationsLow-Rate Digital ComputationEnergy-Scalable AlgorithmsMAC and ProtocolsPower Aware Power Aware Microsensor Microsensor NetworksNetworks)/(10SVleakageTI−∝APIHWOS & MIDDLEWARESWFirst Generation Wireless MicrosensorFirst Generation Wireless MicrosensorBatteryMic.AmpLow-PassFilterADCThresholdDetectorDC/DC ConverterProcessor FIFOFIFOStatic RAM Flash ROMImplemented on an FPGAAntennaClock RecoveryShifterControlRadio ICPower Amp.Sensor Processor Radio206MHz StrongARM 2.4GHz ISM band4-channel acousticOSOS--Controlled Power Down ModesControlled Power Down ModesData collection: 1024 samples at 1kSPS(Processor alternates between idle/active)LOB Calculation(Processor active full-time)Data transmission(Radio transmitter active)Sleep(All systems power down)Time (s)Power (mW)01002003004005000 0.02 0.04 0.06 0.08 0.1 0.12Processor Idle:low = idlehigh = activeProcessor Sleep:low = sleephigh = active or idleDynamic Voltage ScalingDynamic Voltage ScalingDigitally adjustable DC-DC converter powers SA-1110 coreµOS selects appropriate clock frequency based on workload and latency constraintsSA-1110ControlµOSController53.6VVoutDistributed Processing Exploiting DVSDistributed Processing Exploiting DVSA/DSensor 6FFTA/DSensor 2FFTA/DSensor 1FFTCluster HeadFFT1, BF & LOBSensor 7Sensor 6A/DSensor 2Sensor 1Cluster HeadSensor 7A/DA/DFFT7BF & LOBEcomp(variable Vdd) = 15.16 mJApproach 2: Parallelism ameliorates latency constraint FFT: Vdd= 0.9 VBF & LOB: Vdd= 1.3 VEcomp(Vdd=1.5V) = 7Efft+Ebf+ELOB= 27.27 mJ on SA-1100Approach 1: All latency-critical computation at aggregating nodeEnergy Scalable AlgorithmsEnergy Scalable Algorithmsx[n]x[n-1]x[n-2]x[n-N+1]h[0]h[1]h[2]h[N-1]xxxxx[n+1]Original∑−=−=10][][][NkknxkhnyOriginalTransformedFilterEnergy/sample (µJ)Accuracy (%)y[n]TransformedSortedCoeffsRe-order Indexx[n+1]x[n]x[n-1]x[n-2]x[n-N+1]xxxxh[p]h[q]h[r]h[s][Sinha, ISLPED ’00]y[n] Maximize quality for a given energy availabilityLeakage : Low Duty Cycle ConcernLeakage : Low Duty Cycle ConcernFFT Execution TimeTotal Charge flow)/(10SVleakageTI−∝Duty Cycle (%)Total Energy/Switching EnergyLeakage Dominates Switching Energy for Low Duty Leakage Dominates Switching Energy for Low Duty Cycles Cycles ––“Off” State“Off” State--centric Optimizationcentric OptimizationPower Aware RadioPower Aware RadioPLLXilinxRx Power ControlDemod& slice0-20dBmTx Power ControlVregData Fine-grain shutdown through regulators and bias control Variable 6-level PA allows efficient transmission for 10m to 100mSA1110Vreg: Power Down ControlRF StartRF Start--up Energy Overheadup Energy OverheadEnergy per bit (nJ)1000010001001010 100 1000 10000 100000Packet size (bits)Energy Energy = = PPtxtx_electronics_electronics((TTtranmsittranmsit+ + TTstartstart))+ P+ PoutoutTTtransmittransmit Significant loss in energy efficiency for small packet sizesStartup Costs are Fundamental Startup Costs are Fundamental ––Innovative Circuits and Protocols RequiredInnovative Circuits and Protocols RequiredIntegrated SystemIntegrated System--onon--aa--Chip VisionChip VisionPower ConversionEnergyScavengerA/DMEMORYRFDSPSensor Compact Form Factor (mm3–cm3) Requires interconnection of diverse process technologies Low computational requirement, but requires flexibility to adapt to time-varying scenarios Cost, size and energy are the key design constraintsWhat is the best computation/communication fabric?What is the best computation/communication fabric?Why Not Software?Why Not Software?051015202530354045Power (%)Cache Control GCLK EBOX I/O,PLL[Montanaro, JSSC ‘96]Software Energy Dissipation is Dominated by Overhead Software Energy Dissipation is Dominated by Overhead and NOT by Useful Workand NOT by Useful WorkWhat about What about FPGAsFPGAs??4GCLK[3:0]4 4 4ChannelRAM4GCLK[3:0]4 4 44GCLK[3:0]4 4 444GCLK[3:0]PLL & Clock MUXGCTL[3:0]I/O Bank 6I/O Bank 7I/O Bank 3I/O Bank 2I/O Bank 4I/O Bank 5I/O Bank 1 I/O Bank 0LB 4LB 3LB 0ClusterRAMLB 5LB 6LB 7LB 2LB 1PIMClusterRAMChannelRAMChannelRAMChannelRAMChannelRAMChannelRAMChannelRAMChannelRAMChannelRAMChannelRAMChannelRAMChannelRAMLB 4LB 3LB 0ClusterRAMLB 5LB 6LB 7LB 2LB 1PIMClusterRAMLB 4LB 3LB 0ClusterRAMLB 5LB 6LB 7LB 2LB 1PIMClusterRAMLB 4LB 3LB 0ClusterRAMLB 5LB 6LB 7LB 2LB 1PIMClusterRAMLB 4LB 3LB 0ClusterRAMLB 5LB 6LB 7LB 2LB