Constraint Extraction for Pseudo-Functional Scan-based Delay TestingABSTRACTRecent research results have shown that the traditionalstructural testing for delay and crosstalk faults may result inover-testing due to the non-trivial number of such faults that areuntestable in the functional mode while testable in the test mode.This paper presents a pseudo-functional test methodology thatattempts to minimize the over-testing problem of the scan-basedcircuits for the delay faults. The first pattern of a two-patterntest is still delivered by scan in the test mode but the pattern isgenerated in such a way that it does not violate the functionalconstraints extracted from the functional logic. In this paper, weuse a SAT solver to extract a set of functional constraints whichconsists of illegal states and internal signal correlation. Alongwith the functional justification (also called broad-side) testapplication scheme, the functional constraints are imposed to acommercial delay-fault ATPG tool to generate pseudo-functional delay tests. The experimental results indicate that thepercentage of untestable delay faults is non-trivial for manycircuits which support the hypothesis of the over-testingproblem in delay testing. The results also indicate theeffectiveness of the proposed constraint extraction method. I. INTRODUCTIONScan-based delay fault testing has been widelydocumented in the literature. In the past few years,research results have shown that many delay faults arefunctionally untestable while they are structurallytestable. That is, such a fault has no test in the functionalmode while there exists a scan test. The reason why astructurally testable fault might become untestable in thefunctional mode is that various types of functionalconstraints exist due to the functional operations of thelogic. Experimental results reported in [1][2] indicate thatthere is a significant number of Structurally Testablewhile Functionally Untestable (ST-FU) delay faults. Notethat, unlike delay faults, there are relatively few ST-FUstuck-at faults due to the high-testability of stuck-atfaults. For the purpose of diagnosis, all faults should bedetected and identified regardless of whether they arefunctional testable or not. However, for productiontesting, if the percentage of ST-FU delay faults is high,high test coverage of structural delay testing for a scan-based design may result in over-testing and consequentlyincur a yield loss problem. Moreover, at-speed functionaltests [3] have been shown to be more effective atdetecting common manufacturing defects such as delayand crosstalk faults. A couple of further implications can be drawn from theabove statement. First, for delay and crosstalk faults,some DFT methods beyond scan, such as enhanced-scan,test point insertion, etc., which further increase thenumber of ST-FU faults, may make the over-testingproblem even worse. Second, while functional ATPGremains the holy grail of testing, and scan design isessential to achieve a reasonable level of circuitcontrollability and observability, it makes sense togenerate special scan tests to minimize over-testing forproduction testing. Such tests, which are as close as tofunctional tests as possible, we call pseudo-functionaltests. Note that, for diagnosis, different tests can begenerated without consideration of circuit functionality tomaximize the detection of the location of faults, whetherthey are functional testable or not.In this paper, we propose a methodology of identifyinguseful functional constraints, which can be easily imposedon the ATPG process so that the generated patterns aremore like functional patterns. We call this approachpseudo-functional test generation. This approach does notdirectly generate functional patterns. Instead, it restrictsthe ATPG from generating functional meaninglesspatterns. As it is impossible to extract and impose allfunctional constraints, it implies that some of thegenerated pseudo-functional tests might still be non-functional. The goal, therefore, is to find effectivefunctional constraints so that the space restricted by theseconstraints (called pseudo-functional space) is as close tothe functional space as possible.Some of the functional constraints involve illegal states(i.e. unreachable states) in a sequential circuit. Othercommon functional constraints could be the equivalencerelationship and one-hot relationship among a set ofsignals. Such constraints, once identified, can be easilyimposed to an ATPG process without major change to itsalgorithm. For a large circuit, state reachability analysisusing BDD has been shown to be impractical for illegalstate extraction due to the huge state space. On the otherhand, modern SAT solvers [7][9][19] provide anapproximate approach to find as many functionalconstraints, including illegal states and signalcorrelations, as possible. The properties of a sequentialSAT solver [19][20] have been shown to be useful forapplications, such as Bounded Model Checking andEquivalence Checking. In this paper, we employ conceptssimilar to those of bounded model checking to identifyillegal states. The rest of the paper is organized as follows: In SectionII, we explain the background of scan-based delay testingmethodology and a sequential SAT solver, Seq-SAT.Section III presents the ideas of how to utilize thesequential SAT solver to generate functional constraintsin details. Section IV describes the experimentalprocedure and analyzes the experimental results. SectionV concludes the paper.Yung-Chieh LinDept. of ECE, University of California, Santa BarbaraSanta Barbara, CA93106, USA{younglin, lufeng, kyang, timcheng}@ece.ucsb.edu Feng Lu Kai Yang Kwang-Ting ChengII. BACKGROUNDA. Scan-based Delay TestingTesting delay faults in a sequential circuit can be doneusing enhanced scan [4] or standard scan running at-speed, i.e. so-called AC-scan. The AC-scan techniquescans in the first vector and then uses functionaljustification (also called broad-side [22]) or scan shifting(also called skew-load [23]) to produce the second vector[24]. Interested readers can refer to [25] for detaileddiscussion of delay testing. In the functional justificationscheme, the second vector is derived using the capturemode and represents the set of next state values obtainedafter the application of the first vector. On the other hand,scan shifting produces the second pattern of the delay testby the scan mode. As our pseudo-functional methodologyaims at