Lecture 19-1 FETs: Field Effect Transistors• MOSFETs: Metal-Oxide Semiconductor Field Effect Transistors•gates are really polysilicon, not metal•extremely large input resistance•four terminal devices•occupy less area than BJTs --- predominant technology for digital•but do not provide the same gain as BJTs for analog• Used for analog mainly due to the need mixed-signal designs• JFETs: Junction Field Effect Transistors•not as popular as MOSFETs, but behave very similarlyLecture 19-2 Enhancement Mode MOSFETsgatedrainsourcebodyDGBn+n+p• Cross-section view• The basic structure of an enhancement mode mosfetChannelchannel length Lchannel width WMade of polysilicon or rarely metal.The oxide is very thin: e.g. 40 - 15 nm.SLecture 19-3 Enhancement Mode MOSFETsSDGB• NOTE: 4 terminals!!!DGBSn-channel transistoror N-MOSFET(p-type substrate)p-channel transistoror P-MOSFET(n-type substrate)Lecture 19-4 Enhancement Mode MOSFETs• We keep the source and drain p-n junctions off at all times• They contribute small leakage currents, and some nonlinear capacitance• The gate input has practically infinite resistance, and behaves like a capacitorn+n+pSDGBn+n+pSDGBidc=0Lecture 19-5 Enhancement Mode MOSFETs+ -• Depletion regions around the p-n junctions due to the built-in voltages• With all of the voltages set to zero, the S-B-D connections form an NPN BSDGn+n+p• Even with a postive drain voltage, there is no significant current flowBSDGn+n+pvDSLecture 19-6 Enhancement Mode MOSFETs• The gate is used to establish a connection between the source and drain nodes• Postive gate voltage (for this NMOS enhancement transistor):•sets up an electric field from gate to bulk which tends to repel positive charges in the p-type bulk and create a depletion region•negative charge from the source and drain regions is attracted toward the channel by the same electric fieldvGS+ -Lecture 19-7 Enhancement Mode MOSFETs• Gate to bulk acts like a capacitor+ --++ ++- - -QBQGpvGSLecture 19-8 Inversion+ --++ ++---QBQGpvGSQB- --- ---• When the VGS grows high enough, there is not enough holes at the surface to allow for electron recombination. QB becomes a negative fixed charge with density equal to NAof the bulk.• Additional gate voltage causes the free electrons to be drawn to the surface of the channel --- forming an inversion layer. When concentration of electrons at surface equals NA we talk about strong inversion. Additional negative charge now comes from electrons in the channel.+++++Lecture 19-9 Threshold Voltage+ -+ -• The gate voltage required to create strong inversion• If there is a small potential difference between the drain and source, then a current will flow across the inversison layer which acts like a resistoriDiDiS=iDvGSvDS+_+_Lecture 19-10Flatband Voltage -- VFB• There is a depletion region (negative Q) under the channel even with VGS = 0•Due to dangling bonds at the material interfaces and unwanted positive charges at the surfaces and in the oxides• The flatband voltage (generally negative) is the gate voltage required to exactly cancel this charge+ -0vvFB+ -Lecture 19-11Threshold Voltage• The threshold voltage is the flatband voltage plus whatever voltage is required to cause inversion in the channelVBVGVDEPLETION+_n+n++_VoxLecture 19-12Threshold Voltage• Once -QB = NA, then further increases in gate voltage brings about the inversion layer• The depletion charge and voltage becomes fixed at a value called respecitively: QB0 and 2φf• Increases in channel charge correspond to the inversion layer charge, QI VBVG+n+n+QB0+_2φfLecture 19-13Threshold Voltage• Assuming VB and VS are both zero, the threshold voltage is:VB = 0VG+n+n+QB0+_2φfVt0VGthresholdVOXVDEPLVFB++==VS = 0Lecture 19-14Strong Inversion• With a small positive drain voltage, the inversion layer charge will drift from source to drainVB = 0VG > Vt+n+n+QB0VS = 0QI• The conductance of the layer is proportional to VGS - Vt VDS > 0Lecture 19-15Inversion Layer Conductance• Triode or linear region of operation• Example: W=L=1 micron0.0 0.1 0.201020IDS (µA)VDSVGS=2.5VVGS=2.0VVGS=1.5VVGS=1.0VG ~ VGS - VtLecture 19-16Pinch-Off Region --- Saturation• The conductance is not always proportional to VGS-Vt for all VDS• As VDS increases, the bulk charge closer to the drain increases, and the inversion layer charge there decreases• Conductance varies with position along the channelVB = 0VG > Vt+n+n+QBVS = 0QIVDS >> 0Lecture 19-17Pinch-Off Region --- Saturation• As VDS increases further for a fixed VGS, the inversion layer eventually goes to zero at the drain edge of the channel --- pinch-offVB = 0VG > Vt+n+n+QBVS = 0QIVDS >> 0• Current is considered to saturate at this point since further increases in VDS do not increase the current significantlyVDSsat˙VGSVt–≅why?Lecture 19-18Saturation Region• Region of interest for analog design• W=1 micron and L=10 micronsIDS (µA)VDSVGS=2.5VVGS=2.0VVGS=1.5VVGS=1.0VVGS=3.0V0 1 2 3 4 5012345triode regionsaturation regionHere, staturation means “current saturation” which is different than “voltage saturation” in bipolar transistorsLecture 19-19Equations• Triode region equations for enhancement mode N-MOSFETiDK 2 vGSVt–()vDSvDS2–[]=vGSVt≥ vDSvGSVt–≤K12---µnCoxWL-----=AV2-------• For very small vDS, as on page 15, what is rDS?In SPICE: KnµnCox=Lecture 19-20Equations• Saturation region equations for enhancement mode N-MOSFETiDK 2 vGSVt–()vDSvDS2–[]=vGSVt≥vDSvGSVt–≥vDSsatvGSVt–=• Current varies quadratically with vGS iDKvGSVt–()[]2=KW2L------Kn=KnCoxµn=Lecture 19-21Saturation• ForvDSvGSVt–≥0 1 2 3 4 501020IDS (µA)VGS• Large signal model in saturationidSGDKvGSVt–()2+_W=1 micronL=10 micronsVt0= 1 voltKn=2e-5 (A/v2)Lecture 19-22Saturation --- Channel Length Modulation• VDS at the edge of the inversion layer remains fixed at VGS-Vt• But the effective length of the channel decreases with increasing VDS• Especially a factor when channel length is shortVB = 0VG > Vt+n+n+VS = 0VDS >> 0L∆LiDsatKnW2 L ∆L–()-------------------------vGSVt–()2[]=Lecture 19-23Saturation --- Channel Length Modulation• Sometimes expressed in terms of channel length modulation parameteriDsatKnW2L-------------vGSVt–()2[]1 λvDS+()=0 1 2 3 4 5020406080100W=1 micronL=1 micronsVt0= 1 voltKn=2e-5 (A/v2)phi =0.6NA=1e15IDS (µA)VDSVGS=2.5VVGS=2.0VVGS=1.5VVGS=1.0VVGS=3.0V• SPICE can calculate the