CS11 Advanced C++ Spring 2012-2013 Lecture 5Build Automation n Standard development cycle: q Write more code q Compile q Test q Repeat until done… n Automating this process saves lots of time n Intelligent build tools dramatically improve build-times for large software projects q Projects that take minutes or hours to buildmake n make is a standard tool for automating builds q Command-line utility, very ubiquitous! q Takes input files and produces output files, based on a “makefile” q Several versions of make: GNU, BSD, … n make is largely used for C and C++ projects q Sometimes other build tools are used for C/C++ n Perforce Jam is one common alternative n Visual C++ provides nmake command-line build program q Other languages typically have their own build tools n e.g. Ant is frequently used for Java projectsOther Build-Tools n For large projects, other tools are also used alongside make q autoconf, etc. for providing source-portability n Generates a configure script for configuring your program ./configure --prefix = /usr/local/myprog make make install q libtool, etc. for building shared libraries on different platforms q install, rpmbuild, etc. for updating system directories q doxygen, DocBook, etc. for doc-generationMakefiles n The makefile describes build targets q Each target specifies its dependencies q Each target also specifies how to build that target from the dependencies n Typical filename is Makefile or makefile q make looks for these by default q Preferred name is Makefile q Can specify another makefile using -f optionMakefiles (2) n When make is run, a build target can be specified n make raytrace q If no target is specified, the first target in the makefile is run n make q First target is usually named all, and builds everything q Can also specify multiple build targets: n make clean raytrace n Whitespace matters in makefiles! q Indentation is significant! q Tabs must be used for indentation!Example Makefile n Form of rules: target : dependencies commands n Example: lab4 : main.o entry.o except.o config.o g++ -o lab4 main.o entry.o except.o config.o main.o : main.cc entry.hh except.hh config.hh g++ -Wall -c main.cc ... (more rules) clean : rm -f lab4 *.o *~ n Lines indented with tab characters – spaces won’t work! n A line can be continued on next line, by ending it with \ n Can specify multiple commands, if rules are separated by a blank lineReal Build Targets n From our example: main.o : main.cc entry.hh except.hh config.hh g++ -Wall -c main.cc n In this case, main.o is a real file n make will only build what is needed q If target file’s date is older than any dependency, make will rebuild the target n To force a file to be rebuilt, touch it: n touch main.cc q Sets file’s modification-time to current system time q Touching a nonexistent file will create a new empty filePhony Build Targets n From our example: clean : rm -f lab4 *.o *~ n In this case, clean is not a real file n What if there happened to be a file named clean ? q Our rule wouldn’t run! q make would see the “build-target” file, and assume it didn’t have to run n Use .PHONY to say that clean target isn’t a file .PHONY : clean q Now if a file named clean exists, make ignores itChains of Build Rules n make figures out the graph of dependencies lab4 : main.o entry.o except.o config.o g++ -o lab4 main.o entry.o except.o config.o n If any of lab4’s dependencies don’t exist, make will use their build rules to make them main.o : main.cc entry.hh except.hh config.hh g++ -Wall -c main.cc n make will give up if: q A dependency can’t be found, and there’s no build rule that shows how to make itMakefile Variables n Makefiles can define variables OBJS = main.o entry.o except.o config.o q Can use variables in build rules lab4 : $(OBJS) g++ $(OBJS) -o lab4 q $(var-name) tells make to expand the variable n Use variables to avoid listing the same things all over the place q Same as code reuse: only make changes in one place n Makefile variable names are usually ALL_CAPSImplicit Build Rules n make already knows how to build certain targets q Those targets have built-in rules for building them q These built-in rules are called implicit build rules n Example: q A makefile has main.o as a dependency, but no build rule q If main.c exists, make will use gcc to generate main.o q If main.cc exists, make will use g++ to generate main.o n make has quite a few implicit build rules q Read make documentation for more details!Using Implicit Rules n Implicit rules make your makefiles much shorter q Can leave out rules for all the object files OBJS = main.o entry.o except.o config.o lab4 : $(OBJS) g++ -o lab4 $(OBJS) clean : rm -f lab4 *.o *~ .PHONY : clean n What about header file dependencies? q Can specify rules for each object file: main.o : entry.hh except.hh config.hh n No command – these rules just specify dependencies q makedepend auto-generates these from your source files!Definitions of Implicit Rules n Examples of implicit rules: # C compilation implicit rule %.o : %.c $(CC) -c $(CPPFLAGS) $(CFLAGS) $< -o $@ # C++ compilation implicit rule %.o : %.cc $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) $< -o $@ n Variables are used for compiler and options! q CC is C compiler, CXX is C++ compiler q CFLAGS, CXXFLAGS are compiler-options q CPPFLAGS are the preprocessor flags q Default values are for gcc and g++ q Can easily customize these rules, by setting these variables at the top of your makefileDefinitions of Implicit Rules n Implicit rules use patterns: # C compilation implicit rule %.o : %.c $(CC) -c $(CPPFLAGS) $(CFLAGS) $< -o $@ # C++ compilation implicit rule %.o : %.cc $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) $< -o $@ n Special syntax for pattern-matching q % matches the filename q $< is the first