1Chapter 5Chapter 5The LC-3 Instruction Set ArchitectureISA Overview Operate instructions Data Movement instructions Control InstructionsLC-3 data path2Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org. & AssemblyA specific ISA: The LCA specific ISA: The LC--33 We have:– Reviewed data encoding and simple digital concepts– Introduced a general model for computer organization– Discussed a general model for computer execution (the instruction cycle) Now its time to focus on a specific example: The LC-3 ISA– The LC-3 uses a 16-bit word and is word-addressable How large can the LC-3 memory be?– All instructions are represented as 16-bit words– All data is represented as 16-bit words Native Data Type: only 2’s complement integer– The LC-3 uses eight 16-bit GPRs: R0-R7– The LC-3 maintains three 1-bit status codes: N, Z, P3Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org . & Assemb lyLCLC--3 Instructions3 Instructions Three types of instructions– Operate: Manipulate data directly ADD, AND, NOT– Data Movement: Move data between memory and registers LD, LDI, LDR, LEA, ST, STI, STR– Control: Change the sequence of instruction execution BR, JMP/RET, JSR/JSSR, TRAP, RTI Addressing Modes: Immediate (non-memory addressing mode) Register (non-memory addressing modes) Direct (memory addressing mode) Indirect (memory addressing mode) Base+Offset (memory addressing modes)4Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org. & AssemblyLCLC--3 3 Instruction wordInstruction word LC-3 Instructions word: 16 bits– 4-bit opcode => 16 instructions (RISC)– remaining 12 bits specify operand(s), according to the addressing mode proper to each instruction.– Opcode: Specifies what the instruction does IR[15:12]: 4 bits allow 16 instructions specifies the instruction to be executed– Operands: Specifies what the instruction acts on IR[11:0]: contains specifications for: Registers: 8 GPRs (i.e. require 3 bits for addressing) Address Generation bits: Offset (11 or 9 or 6 bits) (more later) Immediate value: 5 bits Examples– ADD DR, SR1, SR2 ; DR  (SR1) + (SR2)[15:12] [11:9] [8:6] [2:0]– LDR DR, BaseR, Offset ; DR  Mem[BaseR + Offset][15:12] [11:9] [8:6] [5:0]5Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org . & Assemb lyAddressing ModesAddressing Modes The LC-3 supports five addressing modes:– the operand is located: in the instruction itself (#1: immediate a.k.a literal) in a register (#2) in memory:– Note: the effective address (ea) is the memory location of the operand– the ea is encoded in the instruction (#3: direct, or PC-relative)– a pointer to the ea is encoded in the instruction (#4: indirect)– a pointer to the ea is stored in a register (#5: base+offset, a.k.a. relative)  LC-3 Operate instructions use only immediate and register modes LC-3 Data movement instructions use all five modes6Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org. & AssemblyOperate Instructions Operate Instructions -- 11 Arithmetic and Logic– Arithmetic: add, subtract, multiply, divide (the LC-3 only has add)– Logic: and, or, not, xor (the LC-3 only has and, not) LC-3: NOT, ADD, AND AND (opcode = 0101) has the same structure as ADD0 0 0 1 0 1 1 0 1 0 0 1 0 10 0 ADD R3 R2dest reg src reg src regR5NOT R3 R2dest reg src reg1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 127Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org . & Assemb ly “Hiding” in the control unit, we find the Processor Status Register (PSR) Many instructions set the condition codes according to their results– Z = result was zero– N = result was negative– P = result was positiveNote that one and only one of these conditions can be trueCondition CodesCondition CodesPriv Priority N Z PPriv Priority N Z P15 10 – 8 2 1 08Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org. & AssemblyNOT: Bitwise Logical NOTNOT: Bitwise Logical NOT UNARY OPERATION Assembler Inst.NOT DR, SR ; DR = NOT SR Encoding1001 DR SR 111111 Examplex977F 1001 0111 0111 11111001 011 101 11 1111NOT R3, R5– Note: Condition codes are set.9Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org . & Assemb lyControl signals Control signals for NOTfor NOTNOT R3, R5• SR1 = 101; ALUK = NOT; GateALU= 1• Wait for signal propagation/sub-cycle tick• DR = 011; LD.REG = 1• Wait for signal propagation/sub-cycle tick• RELEASE ALLx977F 1001 0111 0111 11111001 011 101 11 1111NOT R3, R510Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org. & AssemblyADD: Two's complement 16ADD: Two's complement 16--bit Additionbit Addition BINARY OPERATION Assembler Instruction(register addressing)ADD DR, SR1, SR2 ; DR = SR1 + SR2 (immediate addressing)ADD DR, SR1, imm5 ; DR = SR1 + Sext(imm5) Encoding0001 DR SR1 0 00 SR20001 DR SR1 1 imm5 ExamplesADD R1, R4, R5 0001 001 100 0 00 101ADD R1, R4, # -2 0001 001 100 1 11110– Note: Condition codes are set11Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org . & Assemb lyControl signals for Control signals for ADD (immed5)ADD (immed5)ADD R1,R4,-2• SR1 = 100; SR2MUX = IR; ALUK = ADD; GateALU = 1• Wait for signal propagation/sub-cycle tick• DR = 001; LD.REG = 1• Wait for signal propagation/sub-cycle tick• RELEASE ALLx133E0001 0011 0011 11100001 001 100 1 11110ADD R1,R4,-212Wrig ht State Univ ersity, College of EngineeringDr. Doom, Computer Science & EngineeringCEG 320/520Comp. Org. & AssemblyControl signals for Control signals for ADD (register)ADD (register)ADD R1,R4,R5• SR1 = 100; SR2 = 101; SR2MUX = REGfile; ALUK = ADD; GateALU = 1• Wait for signal propagation/sub-cycle tick• DR = 001; LD.REG = 1• Wait for signal propagation/sub-cycle tick• RELEASE