-cQAma1r7ObHD12vDuc0UPJ1vm4r87ZXyHNXw3qpTvQ8rB060yPncJ07K-U9L6UXX-Z50P4xltSsplJJcBbsFA

A Defect Tolerant Self-organizing Nanoscale SIMD Architecture




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A Defect Tolerant Self-organizing Nanoscale SIMD Architecture Jaidev P. Patwardhan†, Vijeta Johri†, Chris Dwyer‡, and Alvin R. Lebeck† {jaidev,vijeta,alvy}@cs.duke.edu, [email protected] †Department of Computer Science ‡Department of Electrical and Computer Engineering Duke University Duke University Durham, NC 27708 Durham, NC 27708 To Appear, Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems Abstract The continual decrease in transistor size (through either scaled CMOS or emerging nano-technologies) promises to usher in an era of tera to peta-scale integration. However, this decrease in size is also likely to increase defect densities, contributing to the exponen- tially increasing cost of top-down lithography. Bottom-up manu- facturing techniques, like self-assembly, may provide a viable lower-cost alternative to top-down lithography, but may also be prone to higher defects. Therefore, regardless of fabrication meth- odology, defect tolerant architectures are necessary to exploit the full potential of future increased device densities. This paper explores a defect tolerant SIMD architecture. A key fea- ture of our design is the ability of a large number of limited capa- bility nodes with high defect rates (up to 30%) to self-organize into a set of SIMD processing elements. Despite node simplicity and high defect rates, we show that by supporting the familiar data par- allel programming model the architecture can execute a variety of programs. The architecture efficiently exploits a large number of nodes and higher device densities to keep device switching speeds and power density low. On a medium sized system (~1cm2 area), the performance of the proposed architecture on our data parallel programs matches or exceeds the performance of an aggressively scaled out-of-order processor (128-wide, 8k reorder buffer, perfect memory system). For larger systems (>1cm2), the proposed archi- tecture can match the performance of a chip multiprocessor with 16 aggressively scaled out-of-order cores. Categories and Subject Descriptors B.4.3 [Input/Output and Data Communications]: Interconnections (Subsystems); B.6.1 [Logic Design]: Design Styles; C.1.2 [Processor Architectures]: Multiple Data Stream Architectures (Multiprocessors). General Terms Design, Performance, Reliability Keywords self-organizing, SIMD, data parallel, bit-serial, defect tolerance, DNA, nanocomputing. 1 Introduction Manufacturing defects, power density, process variability, tran- sient faults, bulk silicon limits, rising test costs and multibillion dollar fabrication facilities are some of the challenges facing the continued scaling of CMOS. While architectural modifications (e.g., multicore) can provide some short-term relief, the semicon- ductor industry recognizes the importance of these issues and the need to explore long term alternatives to CMOS devices and fabri- cation techniques [18]. One promising alternative is DNA-based self-assembly of nanoscale components using inexpensive laboratory equipment to achieve tera to peta-scale integration. Although much of this tech- nology is in its infancy (i.e., demonstrated in research lab experi- ments), by studying its potential uses for building computing systems, architects can gain a deeper understanding of its limita- tions and opportunities while providing important feedback to the scientists developing the new technologies. DNA-based fabrication produces precise control within a small area (e.g., 9 µm2) enabling the construction of a large number (~109-1012) of small nodes (computational circuits with ~104 tran- sistors) ...





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