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TAMU CSCE 614 - lec05-mem

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CPSC 614:Graduate Computer Architecture Memory Technology Prof. Lawrence RauchwergerMain Memory BackgroundStatic RAM (SRAM)SRAM Read Timing (typical)Slide 5Dynamic RAMBasic DRAM CellAdvanced DRAM CellsSlide 9DRAM OperationsDRAM logical organization (4 Mbit)So, Why do I freaking care?Slide 134 Key DRAM Timing ParametersDRAM Read TimingDRAM PerformanceFast Page Mode DRAMExtended Data Out (EDO)Synchronous DRAMRAMBUS (RDRAM)RDRAM TimingDRAM HistoryMain Memory OrganizationsMain Memory PerformanceIndependent Memory BanksSlide 27Avoiding Bank ConflictsFast Bank NumberDRAMs per PC over TimeNeed for Error Correction!Architecture in practiceFLASH MemoryMore esoteric Storage Technologies?Tunneling Magnetic JunctionMEMS-based StorageMain Memory SummaryCPSC 614:Graduate Computer ArchitectureMemory TechnologyProf. Lawrence RauchwergerBased on lectures byProf. David CullerProf. David PattersonUC BerkeleyMain Memory Background•Random Access Memory (vs. Serial Access Memory)•Different flavors at different levels–Physical Makeup (CMOS, DRAM)–Low Level Architectures (FPM,EDO,BEDO,SDRAM)•Cache uses SRAM: Static Random Access Memory–No refresh (6 transistors/bit vs. 1 transistorSize: DRAM/SRAM 4-8, Cost/Cycle time: SRAM/DRAM 8-16•Main Memory is DRAM: Dynamic Random Access Memory–Dynamic since needs to be refreshed periodically (8 ms, 1% time)–Addresses divided into 2 halves (Memory as a 2D matrix):»RAS or Row Access Strobe»CAS or Column Access StrobeStatic RAM (SRAM)•Six transistors in cross connected fashion–Provides regular AND inverted outputs–Implemented in CMOS processSingle Port 6-T SRAM CellSRAM Read Timing (typical)•tAA (access time for address): how long it takes to get stable output after a change in address.•tACS (access time for chip select): how long it takes to get stable output after CS is asserted.•tOE (output enable time): how long it takes for the three-state output buffers to leave the high- impedance state when OE and CS are both asserted.•tOZ (output-disable time): how long it takes for the three-state output buffers to enter high- impedance state after OE or CS are negated.•tOH (output-hold time): how long the output data remains valid after a change to the address inputs.SRAM Read Timing (typical)stable stable stablevalid valid validtAAtOZ tAAtOEtACStOZtOEMax(tAA, tACS)tOHADDRCS_LOE_LDOUTWE_L = HIGH•SRAM cells exhibit high speed/poor density•DRAM: simple transistor/capacitor pairs in high density formDynamic RAMWord LineBit LineCSense Amp...Basic DRAM Cell•Planar Cell–Polysilicon-Diffusion Capacitance, Diffused Bitlines•Problem: Uses a lot of area (< 1Mb)•You can’t just ride the process curve to shrink C (discussed later)(a) Cross-section(b) LayoutDiffusedbit linePolysiliconplateM1 wordlineCapacitorPolysilicongateMetal word lineSiO2n+Field OxideInversion layerinduced by plate biasn+polypolyUsed Polysilicon-Diffusion CapacitanceExpensive in AreaAdvanced DRAM Cells•Stacked cell (Expand UP)Advanced DRAM Cells•Trench Cell (Expand DOWN)Cell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi SubstrateDRAM Operations•Write–Charge bitline HIGH or LOW and set wordline HIGH•Read–Bit line is precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. –Depending on the charge in the cap, the precharged bitline is pulled slightly higheror lower.–Sense Amp Detects change•Explains why Cap can’t shrink–Need to sufficiently drive bitline–Increase density => increase parasiticcapacitanceWord LineBit LineCSense Amp...DRAM logical organization (4 Mbit)•Square root of bits per RAS/CASColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage CellRow Decoder…So, Why do I freaking care?•By it’s nature, DRAM isn’t built for speed–Reponse times dependent on capacitive circuit properties which get worse as density increases•DRAM process isn’t easy to integrate into CMOS process–DRAM is off chip –Connectors, wires, etc introduce slowness–IRAM efforts looking to integrating the two•Memory Architectures are designed to minimize impact of DRAM latency–Low Level: Memory chips–High Level memory designs.–You will pay $$$$$$ and then some $$$ for a good memory system.So, Why do I freaking care?•1960-1985: Speed = ƒ(no. operations)•1990–Pipelined Execution & Fast Clock Rate–Out-of-Order execution–Superscalar Instruction Issue•1998: Speed = ƒ(non-cached memory accesses)•What does this mean for–Compilers?,Operating Systems?, Algorithms? Data Structures?1101001000198019811982198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU4 Key DRAM Timing Parameters•tRAC: minimum time from RAS line falling to the valid data output. –Quoted as the speed of a DRAM when buy–A typical 4Mb DRAM tRAC = 60 ns–Speed of DRAM since on purchase sheet?•tRC: minimum time from the start of one row access to the start of the next. –tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns•tCAC: minimum time from CAS line falling to valid data output. –15 ns for a 4Mbit DRAM with a tRAC of 60 ns•tPC: minimum time from the start of one column access to the start of the next. –35 ns for a 4Mbit DRAM with a tRAC of 60 nsADOE_L256K x 8DRAM9 8WE_LCAS_LRAS_LOE_LA Row AddressWE_LJunkRead AccessTimeOutput EnableDelayCAS_LRAS_LCol Address Row Address JunkCol AddressD High Z Data OutDRAM Read Cycle TimeEarly Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L•Every DRAM access begins at:–The assertion of the RAS_L–2 ways to read: early or late v. CAS Junk Data Out High ZDRAM Read TimingDRAM Performance•A 60 ns (tRAC) DRAM can –perform a row access only every 110 ns (tRC) –perform column access (tCAC) in 15 ns, but time between column accesses is at least 35 ns (tPC). »In practice, external address delays and turning around buses make it 40 to 50 ns•These times do not include the time to drive the addresses off the microprocessor nor the memory controller overhead!•Can it be made faster?Fast Page Mode DRAM•Page: All bits on the same ROW (Spatial Locality)–Don’t need to wait for wordline to recharge–Toggle CAS with new column addressExtended Data Out (EDO)•Overlap Data output w/ CAS toggle–Later brother: Burst EDO (CAS toggle used to get next addr)Synchronous DRAM•Has a clock input.–Data output is in bursts w/ each element


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