finalproject4ALU (22 pages)

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finalproject4ALU



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finalproject4ALU

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Pages:
22
School:
San Jose State University
Course:
Ee 166 - Design of CMOS Digital Integrated Circuits

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4bit ALU Arithmetic Logic Unit Lam Nguyen Vinh Nguyen The Dao Advisor Dr David Parent Date 12 05 05 1 Agenda 1 Abstract 2 Introduction Why Background Information 3 Project Summary Schematic Layout LVS report Longest Path Calculations Lessons Learned 4 Summary 5 Acknowledgements 2 Abstract Our designed project 4 ALU performs the following functions AND OR XOR ADDER Area 390 m 590 m 0 23 m2 3 Introduction ALU is a basic fundamental unit of any computing system Understanding how an ALU is designed and how it works is a benefit to build any advanced logic circuits Using this experience we can have a basic to design a more complex IC 4 Project Details Create Schematics and layouts for And Or Xor Adder flipflop and Mux in the Cadence tool Test the schematics by using test bench Create Schematic and layout for 1 bit ALU Run DRC extract and LVS for 1 bit ALU Connect Cout of the first bit to Cin of the second bit and continue to have 4 bit ALU Run the DRC extracted LVS and simulation to check the final design 5 1bit ALU Logic DFF Logic DFF The design uses the concept of parallel operations 6 4 to 1 Mux S0 0 1 0 1 S1 0 0 1 1 Output And Or Xor Adder ALU handles two inputs of 4 bits each to produce a required output based on the output selection 7 4 1 Mux Wp 9 Wn 4 5 8 4 1Mux Test Bench Time delay 0 5ns 9 1 bit Adder Wp 7 8 Wn 9 10 4 bit Full Adder Time delay 1 5ns 11 DFF Layout 12 DFF Test Bench Time delay 1 2ns 13 Longest Path Calculations 14 4 ALU Schematic 15 4 ALU Layout 16 Schematic Test Bench 17 LVS 18 Simulation Select S0 1 and S1 1 to have the longest path 19 Lessons Learned Using Cadence tool Designing an integrated circuit to met a specification Fixing errors from LVS report and extracted schematic file Using a same height for each layout cell to reduce the area 20 Summary Our designed 4 bit ALU can operate for the following operations And Or Xor Add Our project has 372 transistors and 20 terminals The delay propagation is 5ns Area 390 m 590 m 0 23 m2 21



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