1Simplification of Sequential CircuitsEquivalent StateState ReductionImplication TableMinimization ProcedureEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 2Simplification of Sequential circuitsEquivalent State :States S1,S2…..Sj are equivalent if and only if for every possible input sequence, the same output will be produced regardless of whether S1,S2…..Sjis the initial statesEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 3Pair wise Siand Sj are equivalent if and only if for every possible input Ip,1. Output produced by Si is equal to output produced by Sj2. Next state Skand Slare equivalentSimplification of Sequential circuitsEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 4A Equivalent Relation on S is-Symmetric SiR Sj => SjR Sj-ReflexiveSiR Sifor all i- TransitiveSiR Sjand Sj R Sk => Siand SkSimplification of Sequential circuitsEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 5State Reduction:To determine equivalent states:1. Inspection2. Partitioning3. Implication TableEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 6• Inspection: Trivial• Partitioning:Pk= (S1S3)(S2S4)(S5),S1and S3are k-equivalent.State Reduction:EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 7State Reduction:Partition P1a. Two or more status in the same block iff their output is identical for each input.P1= (ABC)(DE)A/1E/0EB/1D/0DE/0B/1CE/0C/1BB/0C/1A10EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 8b. Place 2 or more states in the same block iff for each input value their next states all lie in a single block of Pk-1State Reduction:P2= (A)(BC)(DE)(ABC) x=0(ABC)(ABC) x=1(ABC)(DE)EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 9c. When Pk+1 = PkÆ stop Æ Pk= equivalent partition.P3 = (A)(BC)(D)(E)State reduction:EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 10Implication TableConsider the following example of a state table.0 0A FG0 1G CF0 0B GE0 0D FD0 0F EC0 1D CB0 0A BAZ‘0’‘1’NS‘0’‘1’PSEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 11is caused by conflict in outputBFBFDFEFBFEGAFEFBCDEFGA B C D E F AF BEAB BGDGBD FGADAB FGImplication TableEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 12Implication TableBFBFDFEFBFEGAFEFBCDEFGA B C D E F AF BEAB BGDGBD FGADAB FGEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 13Implication TableBFBFDFEFBFEGAFEFBCDEFGA B C D E F AF BEAB BGDGBD FGADAB FGEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 14Implication Table()}()( )( )()(){}ECBFADGmSBFFBAGDGDGADA=∴⇒≡⇒≡≡≡⎪⎭⎪⎬⎫EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 15State Reduction of Incompletely Specified Circuitz Definition – State Siand Sjare compatible iff:z Outputs produced by Siand Sjare the same for each possible input Ip.z The next state of Siand Sjmust e compatible for each possible input Ip.EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 16State Reduction of Incompletely Specified Circuitz Definition:z A maximal compatible is a compatible class that will not remain a compatible class if any state not in the class is added.z Compatible class ≡ Set of compatible statesEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 17ExampleState Tablex01AA/- C/1BB/- A/-CG/- E/0DC/1 C/-EA/1 C/-FD/- A/-GG/- G/-HH/- D/-EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 18Implication TableACBGAEAC√BCACABACBDCG AG EG CG CDAG DGCG AGCGCEAGDGAEAD GH CH AH DH DE CD CD ADDGACCD ADAC ACAD ACBCDEFGHA B C D E F GEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 19Compatibility ClassesG (GH)F (GH)(FG)E (EG)(EH)(GH)(FG)E (FG)(EGH)D (DG)(FG)(EGH)C (CG)(CF)(CE)(CD)(DG)(FG)(EGH)C (CEG)(CDG)(CFG)(EGH)B (BC)(BG)(CEG)(CDG)(CFG)(EGH)A (AE)(AG)(AH)(BC)(BG)(CEG)(CDG)(CFG)(EGH)A (AEG)(AGH)(AEH)(BCG)(CEG)(CDG)(CFG)(EGH)A (AEGH)(BCG)(CDG)(CEG)(CFG)EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 20Incompatibility ClassesG -F(FH)E (FH)(EF) D (FH)(EF)(DH)(DF)(DE)D (FH)(DH)(DEF)C (CH)(FH)(DH)(DEF)B (BH)(BF)(BE)(BD)(CH)(FH)(DH)(DEF)B (BH)(BDEF)(CH)(FH)(DH)B (BDEF)(CH)(BDFH)A (AB)(AC)(AD)(AF)(BDEF)(CH)(BDFH)A (ABDF)(AC)(BDEF)(CH)(BDFH)EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 21Merger Diagram for the maximal compatiblesAEFGDCBHEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 22Minimization Conditions1. Completeness (coverage)2. Consistency (closure)3. Minimality (smallest number of compatibility classes)EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 23Minimization Procedurez The upper bound U on the number of states in the minimal circuit is:U = minimum {NSMC, NSOC}NSMC: number of sets of maximal compatiblesNSOC: number of states in the original circuitEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 24Minimization Procedurez The lower bound L on the number of states in the minimal circuit is:L = maximum {NSMC1, NSMC2, …, NSMCi, …}NSMCi: number o states in the ith group of the set of maximal incompatibles of the original circuitEE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy Davis Lecture 03 25ExampleCLOSURE TABLE REDUCED STATE TABLEXX01 0 1(AEGH) AGH CDG A’ A’/1 C’/1(BCG) BG AEG B’ B’/- A’/0(CDG) CG CEG C’ B’,C’,D’,E’/1 D’/0(CFG) DG AEG D’ A’/1 D’/0(CEG) AG CEG E’ C’/- A’/0EE270 Simplification of Sequential Circuits Dr. Tri Caohuu © 2006 Andy