For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEX12 Design Compiler InterfaceTo use the Synopsys Design Compiler with VHDL Compiler,Design Compiler calls VHDL Compiler to translate a VHDLdescription to a netlist equivalent, then synthesizes that logicinto gates in a target technology. The synthesized circuit canthen be written back out as a netlist (or other technology-specific format), or as a technology-independent VHDLdescription.Design Compiler can also call VHDL Compiler to write outdesigns in VHDL format, regardless of the design’s originalformat.To explore the design compiler interface, familiarize yourselfwith these topics: Starting Design Compiler Processing the VHDL source files Using Analyze and Elaborate with VHDL source files Writing out VHDL files Optimizing with Design CompilerVHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXDesign Analyzer is the Synopsys graphic interface to its tools.Design Analyzer reads in, synthesizes, and writes out VHDLsource files, among others. Design Analyzer calls DesignCompiler for the functions.When you view a synthesized schematic in Design Analyzer,you can use the text viewer to see the correspondencebetween VHDL source code and its synthesized entities andgates. For more information, see the Design Analyzer Refer-ence Manual.This chapter describes the commands and variables you useto read VHDL designs. It also explains how to specify synthesisattributes and constraints for compilation, and how to writeout designs in VHDL format.Note:This chapter assumes that you are familiar with DesignCompiler concepts, especially synthesis attributes andconstraints. For more information, see the Design Com-piler Family Reference Manual.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXStarting Design CompilerDesign Compiler has two interfaces: a command-basedinterface (dc_shell), and a graphic interface (design_analyz-er).Starting the Command Interface (dc_shell )Start the Design Compiler command interface by enteringthe invocation command dc_shell at your UNIX prompt:% dc_shell Design Compiler (TM) ECL Compiler (TM) VHDL Compiler (TM) Library Compiler (TM) Test Compiler (TM) Version v3.0 Copyright (c) 1988–1992 by Synopsys, Inc. ALL RIGHTS RESERVEDThis program is proprietary and confidential informationof Synopsys, Inc. and may be used and disclosed only as authorizedin a license agreement controlling such use and disclosure.Initializing...When Design Compiler is through initializing, the command-line prompt appears:Initializing...dc_shell>VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXStarting Design AnalyzerStart Design Analyzer by entering the invocation commanddesign_analyzer at your UNIX prompt, in an X Window com-mand window. Like most UNIX programs, you can use theampersand (&) to run Design Analyzer in the background:% design_analyzer &The main Design Analyzer window appears. For completeinformation on using Design Analyzer, see the Design AnalyzerReference Manual.Design Analyzer also provides access to the dc_shell com-mand interface, through the Setup menu’s Command Windowselection.Processing the VHDL Source FilesYou can process VHDL source files in one of two ways: useDesign Compiler’s analyze and elaborate commands toread in VHDL design files, or use the read command.Version 3.1 and subsequent versions support common analy-sis for synthesis and simulation. If you analyze for synthesis, youdo not need to reanalyze for the Synopsys simulator.WARNINGIf you use design libraries other than WORK, the readcommand is not backward compatible. To make theread command compatible, map all design libraries toWORK.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXUsing Analyze and Elaborate with VHDL Source FilesUse the analyze and elaborate commands to process VHDLsource files. The advantage of using analyze and elaborateis that the out-of-date source files need to be reanalyzedwhen changes are made to the VHDL source. Also, theanalyze and elaborate commands are the only way thatdesign libraries other than WORK can be used. For more in-formation on design libraries, see Appendix D.Analyzing and Elaborating a Single VHDL Source FileTo process a VHDL design when the entire design is in one file,in this case alu.vhd, use the analyze and elaborate com-mands as follows:dc_shell> analyze –format vhdl alu.vhddc_shell> elaborate aluAnalyzing and Elaborating Multiple VHDL Source FilesTo process a VHDL design that is described in more than onefile, enclose the list of filenames in braces ({}):dc_shell> analyze –format vhdl {alu.vhd, control.vhd}dc_shell> elaborate aluVHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXAnalyzing HDL PackagesVHDL packages can be analyzed like any other source file.However, if the package is not being changed with everyanalyze, it is probably more convenient to analyze the pack-age into a design library. After a package is analyzed into adesign library, it needs to be reanalyzed only when the pack-age becomes out-of-date.The following example shows how to analyze packages intoa library. The packages in types.vhd and functions.vhd areanalyzed into the lib1 library.dc_shell> analyze –f vhdl –library lib1 {types.vhd functions.vhd}To use a package out of a library, you need to include some-thing similar to the following code in the VHDL source:library lib1;use lib1.types.all;use lib1.functions.all;entity ALU is. . .The types and functions packages are then automaticallyloaded out of library lib1 if they exist. For information on howto use design libraries, see Appendix D.Note:IEEE and synopsys library packages have been analyzedfor you. You need to reanalyze only if you makechanges.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXReading VHDL Source FilesTo read VHDL source files into Design Analyzer, use the