Integrated Link/CPU Voltage Scaling for Reducing Energy Consumption ofParallel Sparse Matrix Applications∗Seung Woo Son, Konrad Malkowski, Guilin Chen, Mahmut Kandemir, Padma RaghavanThe Pennsylvania State UniversityDepartment of Computer Science and EngineeringUniversity Park, PA 16802 USA{sson,malkowsk,guilchen,kandemir,raghavan}@cse.psu.eduAbstractReducing power consumption is quickly becoming afirst-class optimization metric for many high-performanceparallel computing platforms. One of the techniques em-ployed by many prior proposals along this direction is volt-age scaling and past research used it on different compo-nents such as networks, CPUs, and memories. In contrastto most of the existent efforts on voltage scaling that tar-get a single component (CPU, network or memory com-ponents), this paper proposes and experimentally evaluatesa voltage/frequency scaling algorithm that considers CPUand communication links in a mesh network at the sametime. More specifically, it scales voltages/frequencies ofboth CPUs in the network and the communication linksamong them in a coordinated fashion (instead of one af-ter another) such that energy savings are maximized with-out impacting execution time. Our experiments with severaltree-based sparse matrix computations reveal that the pro-posed integrated voltage scaling approach is very effectivein practice and brings 13% and 17% energy savings overthe pure CPU and pure communication link voltage scal-ing schemes, respectively. The results also show that oursavings are consistent with the different network sizes anddifferent sets of voltage/frequency levels.1. IntroductionPower consumption is becoming a critical issue for high-end computing platforms due to several factors includingcosts, space, reliability, and maintenance. Consequently, re-cent research efforts from different groups in both academiaand industry have focused on techniques that help us ac-curately model and reduce power consumption of differenthardware components in a large computing infrastructure.These studies, details of which are discussed in Section 2 ,include CPU p ower optimizations, memory banking andlow-power operating mode management, network powerminimization, and energy-oriented disk I/O optimizations.∗This work is supported in part by NSF grants CCF 0444158, CNS0406340, CCF 0444345, and CCF 0102537.Voltage and frequency scaling has been identified bypast research as one of the most effective ways o f reduc-ing CPU power [10, 28]. More recently, there have beenproposals [25, 29] that apply voltage/frequency scaling tonetwork links to save communication power. However, toour knowledge, none of the prior efforts in the domain ofhigh-performancecomputing considered using voltage scal-ing on both CPUs and communication links of a given par-allel architecture in a coordinated fashion to save power.The work described in this paper is a step in this direction.More specifically, focusing on sparse matrix computationsthat can be represented as trees, this paper studies the poten-tial benefits that can be accrued when using CPU and com-munication link voltage/frequency scaling in a coordinatedfashion. To achieve this, we p ropose and experimentallyevaluate a voltage/frequency scaling algorithm.An important characteristic of the proposed algorithm isthat it tunes the CPU and link voltages carefully so that wecan obtain the potential power savings without increasingthe original execution time, i.e., the time taken when novoltage scaling is employed. The important point is that wescale the voltages of CPUs and links considering the impactof doing so on each other; this is radically different froman alternate approach that applies CPU voltage scaling af-ter communication link voltage scaling or vice versa. Totest the effectiveness of our approach, we applied it to a setof tree-based sparse matrix computations running on a two-dimensional mesh network and compared it two alternateschemes, one that applies voltage scaling only to CPUs andthe other one that applies voltage scaling to only communi-cation links. Our experiments reveal that the proposed inte-grated voltage/frequency scaling approach is very effectivein practice and brings 13% and 17% energy savings overthe pure CPU and pure co mmunication link voltage scalingschemes. The results also show that our savings are con-sistent with the different network sizes and different sets ofvoltage/frequency levels.The remainder of this paper is structured as follows. Inthe following section, we describe the related work on volt-age scaling in the context of the interconnection networkand processors. Section 3 explains the tree based compu-tation model for parallel sparse matrix solvers. Our inte-1-4244-0054-6/06/$20.00 ©2006 IEEEgrated link/CPU voltage scaling algorithm is presented inSection 5. Section 6 presents an experimental evaluation ofthe proposed algorithm. We conclude the paper in Section 7with a summary of our major contributions.2. Related WorkSeveral studies in the past have proposed dynamic volt-age scaling (DVS) techniques for reducing energy con-sumption of communication links in the NoC (Network-on-Chip) based systems and high-end multiprocessor systems[25, 26, 29]. The main idea behind these approaches is toscale down the voltage/frequency of communication linkswhen there is enough communication slack (i.e., the amountof latency by which communication can be delayed withoutaffecting overall execution time) observed or predicted. Inorder for these DVS techniques to be feasible, Kim et al [19]proposed serial links that can operate under various linkvoltage/frequency levels. Employing links with variablevoltage/frequency, Shang et al [25] presented and evaluateda history-based DVS scheme for the communication links.Worm et al [29] proposed an adaptive low-power transmis-sion technique for on-chip networks, whereas Shin et al [26]discussed a task mapping technique based on genetic algo-rithms to utilize voltage scalable links for saving energy inNoC based systems. Besides DVS techniques for commu-nication links, several techniques that shut down unused orunderutilized links have proposed. Kim et al [18] proposeda dynamic link shutdown (DLS) technique for chip-to-chipnetworks. Soteriou et al [27] explored the design space forcommunication links with tu rn on/off capability.In addition to these efforts that target at reducing p owerconsumption in communication links, there are also studiesthat target at