For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEX11 VHDL Compiler DirectivesSynopsys has defined several methods of providing circuitdesign information directly in your VHDL source code. Using VHDL Compiler directives, you can direct thetranslation from VHDL to components with special VHDLcomments. These synthetic comments turn translation onor off, specify one of several hard-wired resolution meth-ods, and provide a means to map subprograms tohardware components. Using Synopsys-defined VHDL attributes, you can addsynthesis-related signal and constraint information toports, components, and entities. This information is usedby Design Compiler during synthesis. Using embedded scripts, you can add one or moreDesign Compiler commands to your VHDL source withspecial VHDL comments. When your design is read intoDesign Compiler, VHDL Compiler translates your design.Embedded commands are then executed by DesignCompiler.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXTo familiarize yourself with VHDL Compiler directives, considerthe following topics: Notation for VHDL Compiler Directives VHDL Compiler Directives Synthesis Attributes and Constraints Embedded Constraint and Attribute CommandsNotation for VHDL Compiler DirectivesVHDL Compiler directives are special VHDL comments (syn-thetic comments) that affect the actions of the SynopsysVHDL Compiler or Design Compiler. These comments are justa special case of regular VHDL comments, so they are ig-nored by other VHDL tools. Synthetic comments are used onlyto direct the actions of VHDL Compiler.Synthetic comments begin just as regular comments do, withtwo hyphens (– –). If the word following these characters ispragma or synopsys, the remaining comment text is interpretedby VHDL Compiler as a directive.Note:VHDL Compiler displays a syntax error if an unrecognizeddirective is encountered after – – synopsys or – – prag-ma.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXVHDL Compiler DirectivesThe three types of directives are Translation stop and start Directives– – pragma translate_off– – pragma translate_on– – pragma synthesis_off– – pragma synthesis_on Resolution function directives– – pragma resolution_method wired_and– – pragma resolution_method wired_or– – pragma resolution_method three_state  Component implication directives– – pragma map_to_entity entity_name– – pragma return_port_name port_nameThere are other directives such as map_to operator which areused to drive inference of HDL operators such as ”*”, ”+”, and”–”. Refer to the DesignWare Developer Guide for moreinformation.Translation Stop and Start DirectivesTranslation directives stop and start VHDL Compiler’s transla-tion of a VHDL source file.– – pragma translate_off– – pragma translate_onThe translate_off and translate_on directives instruct VHDLCompiler to stop and start synthesizing VHDL source code.The VHDL code between directives is, however, checked forsyntax.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXFor situations where you need VHDL compiler to completelyignore the text in between directives, set the variablehdlin_translate_off_skip_text = true. Setting this variableensures that VHDL Compiler treats the text between thedirectives as comments. This additional behavior of trans-late_off and translate_on has been added for reasons ofbackward compatibility and should be used with caution.Translation is enabled at the beginning of each VHDL sourcefile. You can use translate_off and translate_on directivesanywhere in the text. If the directive hdlin_trans-late_off_skip_text is set to true, three things will happen. Code being analyzed using vhdlan –spc or dc_shellanalyze might produce unexpected results when simu-lated in VSS. This is because VSS does not simulate anyVHDL text between the directives. Synopsys software ignores all the VHDL code betweenthe directives. If you try to simulate a VHDL design that has this variableon and also uses the directives, the Synopsys simulatordisplays a warning and continues. Synopsys does notguarantee that the same code will simulate on anyother simulator.The synthesis_off and synthesis_on directives are the recom-mended mechanisms for hiding simulation-only constructsfrom synthesis. Any text between these directives is checkedfor syntax, but no corresponding hardware is synthesized. Thebehavior of the synthesis_off and synthesis_on directives isnot affected by the variable hdlin_translate_off_skip_text.The behavior of the directives translate_off/on and synthe-sis_off/on is the same, if the variable hdlin_trans-late_off_skip_text is false.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXExample 11–1 shows how you can use the directives to pro-tect a simulation driver.Example 11–1 Using synthesis_on and synthesis_off Directives–– The following test driver for entity EXAMPLE–– should not be translated:––– – pragma synthesis_off–– Translation stopsentity DRIVER isend;architecture VHDL of DRIVER is signal A, B : INTEGER range 0 to 255; signal SUM : INTEGER range 0 to 511; component EXAMPLE port (A, B: in INTEGER range 0 to 255; SUM: out INTEGER range 0 to 511); end component;begin U1: EXAMPLE port map(A, B, SUM); process begin for I in 0 to 255 loop for J in 0 to 255 loop A <= I; B <= J; wait for 10 ns; assert SUM = A + B; end loop; end loop; end process;end;– – pragma synthesis_on–– Code from here on is translatedVHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXentity EXAMPLE is port (A, B: in INTEGER range 0 to 255; SUM: out INTEGER range 0 to 511);end;architecture VHDL of EXAMPLE isbegin SUM <= A + B;end;Resolution Function DirectivesResolution function directives determine the resolution func-tion associated with resolved signals