UNI CS 2420 - Roman Architecture: Activity Four (12 pages)

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Roman Architecture: Activity Four



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Roman Architecture: Activity Four

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Pages:
12
School:
University of Northern Iowa
Course:
Cs 2420 - Computer Architecture
Computer Architecture Documents
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Instruction set Design Issues what is the ML instruction format s ML instruction Opcode Dest Operand Source Operand 1 1 Which instructions to include How many Complexity simple ADD R1 R2 R3 complex e g VAX MATCHC substrLength substr strLength str looks for a substring within a string 2 Which built in data types integer floating point character etc 3 Instruction format Length fixed variable number of address 2 3 etc field sizes 4 Number of registers 5 Addressing modes supported how are the memory addresses of variables data determining Lecture 2 1 Number of Operands 3 Address 2 Address MOVE X b Y MOVE X b Y ADD X b Y Z SUB X b Y Z MUL X b Y Z DIV X b Y Z ADD X b X Y ADD X b X Y MUL X b X Y DIV X b X Y 1 Address Accumulator machine LOAD M STORE M ADD M SUB M MUL M DIV M 0 Address Stack machine 1 Address Accumulator machine LOAD B MUL C ADD A STORE D 0 Address Stack machine PUSH M POP M ADD SUB MUL DIV D A B C 3 Address 2 Address MUL D B C ADD D D A MOVE D B MUL D C ADD D A PUSH B PUSH C MUL PUSH A ADD POP D Load Store Architecture operands for arithmetic operations must be from to registers LOAD R1 B LOAD R2 C MUL R3 R1 R2 LOAD R4 A ADD R3 R4 R3 STORE R3 D Lecture 2 2 Flow of Control How do we jump around in the code to execute high level language statements such as if then else while loops for loops etc Two Paths Possible Jump over Execute TRUE if x y then FALSE then body then body if x y code of then body Jump over else Execute else body code of else body else body always after end if then body Conditional branch used to jump to else if x y Unconditional branch used to always jump end if Labels are used to name spots in the code memory if else and end if in below example Test and Jump version of the if then else Used in MIPS if bge x y else j end if else end if Lecture 2 3 Set Then Jump version of the if then else Used in Pentium if cmp x y jge else j end if else end if The cmp instruction performs x y with the result used to set the condition codes SF Sign Flag set if result is 0 ZF Zero Flag set if result 0 CF Carry Flag set if unsigned overflow OF Overflow Flag set if signed overflow For example the jge instruction checks to see if ZF 1 or SF 1 i e if the result of x y is zero or negative Lecture 2 4 Machine Language Representation of Branch Jump Instructions How are labels e g end if in the code located a direct absolute addressing the memory address of where the label resides is put into the machine language instruction EA effective address direct e g assume label end if is at address 800016 ML instruction AL instruction j end if Opcode 8000 end if How relocatable is the code in memory if direct addressing is used How many bits are needed to represent a direct address b Relative PC relative base register addressing where the PC is the implicitly referenced register ML instruction AL instruction while bge R8 R9 end while b while end while Lecture 2 5 PC 4000 Opcode 8 9 40 end while label 40 addresses from bge Opcode 40 PC 4040 Unconditional pc relative branches are possible too Machine Language Representation of Variables Operands How are labels e g sum score etc in the code located a Register operand is contained in a register ML instruction AL instruction add r9 r4 r2 Opcode 9 4 2 b Direct absolute addressing the memory address of where the label resides is put into the machine language instruction EA effective address direct e g assume label sum is at address 800016 and score is at address 8004 AL instruction add sum sum score ML instruction Opcode 8000 32 bits 8000 32 bits 8004 32 bits c Immediate part of the ML instruction contains the value AL instruction addi r9 2 Lecture 2 6 ML instruction Opcode 9 2 d Indirect operand is pointed at by an address in a memory ML instruction AL instruction addri r9 A r2 Opcode 9 8000 2 ML instruction Opcode 9 8000 2 4000 8000 EA A 4000 Register Indirect operand is pointed at by an address in a register AL instruction addri r9 r4 r2 Memory Register File ML instruction Opcode 9 4 4000 2 r4 EA r4 Lecture 2 7 4000 Base register addressing Displacement operand is pointed at by an address in a register plus offset AL instruction Load r9 40 r2 Memory ML instruction Opcode 9 40 Register File 2 r2 4000 4040 4000 40 EA r2 40 Lecture 2 8 Stack Pointer Register 29 sp Data Global Heap Unused 5 X 3 Y 0 SUM Program Area A Program s Address Space Stack Often the reference register is the stack pointer register to manipulate the run time stack or a global pointer to a block of global variables Load R3 Y Load R2 X Add R1 R2 R3 Store R1 SUM Global Pointer Register 28 gp Program Counter pc f Indexing ML instruction contains a memory address and a register containing an index ML instruction AL instruction addindex r9 A r2 Opcode 9 Reg File ML instruction Opcode 9 8000 EA A r2 2 r2 10 8000 8010 Useful for array access Lecture 2 9 8000 2 Reduced Instruction Set Computers RISC Two approaches to instruction set design 1 CISC Complex Instruction Set Computer e g VAX or IBM 370 1960 s Make assembly language AL as much like high level language HLL as possible to reduce the semantic gap between AL and HLL Alleged Reasons reduce compiler complexity and aid assembly language programming compilers not too good at the time e g they did not allocate registers very efficiently reduce the code size memory limited at this time improve code efficiency complex sequence of instructions implemented in microcode e g VAX MATCHC substrLength substr strLength str that looks for a substring within a string Characteristics of CISC high level like AL instructions variable format and number of cycles many addressing modes VAX 22 addressing modes Problems with CISC complex hardware needed to implement more and complex instructions which slows the execution of simpler instructions compiler can rarely figure out when to use complex instructions verified by studies of programs variability in instruction format and instruction execution time made CISC hard to pipeline 2 RISC mid 1980 s Addresses these problems to improve speed Table 9 1 characteristics of some CISC and RISC processors Lecture 2 10 Table 9 1 characteristics of some CISC and RISC processors Lecture 2 11 General Characteristics of RISC emphasis on optimizing instruction pipeline a one instruction …


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