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Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification



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Cycle and Phase Accurate DSP Modeling and Integration for HW SW Co Verification Lisa Guerra Joachim Fitzner Dipankar Talukdar Chris Schl ger Bassam Tabbara Vojin Zivojnovic Conexant Systems 4311 Jamboree Rd MC 510E 602 Newport Beach CA 92660 USA lisa guerra dipankar talukdar conexant com AXYS GmbH UC Berkeley EECS Dept Kaiserstr 100 211 150 Cory Hall 52134 Herzogenrath Germany Berkeley CA 94720 USA jf cs vz axys de tbassam eecs berkeley edu ABSTRACT We present our practical experience in the modeling and integration of cycle phase accurate instruction set architecture ISA models of digital signal processors DSPs with other hardware and software components A common approach to the modeling of processors for HW SW co verification relies on instruction accurate ISA models combined i e wrapped with the bus interface models BIM that generate the clock phase accurate timing at the component s interface pins However for DSPs and new microprocessors with complex architectural features this approach is from our perspective not acceptable The additional extensive modeling of the pipeline and other architectural details in the BIM would force us to develop two detailed processor models with a complex BIM API between them We therefore propose an alternative approach in which the processor ISAs themselves are modeled in a full cycle phase accurate fashion The bus interface model is then reduced to just modeling the connection to the pins Our models have been integrated into a number of cycle based and event driven system simulation environments We present one such experience in incorporating these models into a VHDL environment The accuracy has been verified cycle by cycle against the gate RTL level models Multiprocessor debugging and observability into the precise cycleaccurate processor state is provided The use of co verification models in place of the RTL resulted in system speedups up to 10 times with the cycle accurate ISA models themselves reaching performances of up to 123K cycles sec 1 INTRODUCTION The trend of developing increasingly complex systems under shrinking time to market conditions continues Typical currentday single chip electronic system implementations include a mix of a number of microcontroller DSP shared memory dedicated logic and interconnect components With increased hardware and software design complexity greater use of components from various design teams and third parties and rising number of gates per pin verification has emerged as a critical bottleneck surrounding the system on chip design paradigm In addressing this verification bottleneck concurrent simulation of full systems on chip with interacting hardware and software is now widely recognized as an important and viable verification approach Co simulation verification of hardware and software has been proposed for a number of environments such as 8 3 12 5 10 13 4 15 2 and is also offered commercially by companies such as Mentor Graphics 9 Synopsys 14 and others In this work our interest is system co simulation used during cycle accurate system verification after the system architecture has been selected and hardware and software models have been developed Co simulation enables the verification of actual processor application code running on ISA processor models in conjunction with accurate models of the remainder of the hardware system In general for cycle accurate processor modeling there have been efforts which develop C C based cycle accurate ISA models to verify against the RTL models e g for the UltraSparc 11 and CRISP 32 bit RISC microprocessors 6 On the other hand in the co verification domain the most common approach for cycle phase accurate modeling uses instruction based ISA models extended by simple interface models commonly referred to as bus interface models BIM or wrappers which interpret external interaction events and thereby generate cycle phase accurate simulation traces at the component s pins This method is used for example in the ARM7 processor model 7 integrated into commercial HDL based environments such as 14 and 9 For architectures with a simple timing this can provide a satisfactory level of accuracy under most circumstances Recent DSP architectures and a growing number of new microcontrollers however have deep pipelines with greater memory access bandwidth memory accesses distributed over multiple stages and complex stalling logic For these types of processors bus interface models become very complex and must include modeling of pipeline and architecture information in order to recover the necessary timing Our contribution described here offers an alternative to detailed interface models we model the processor ISA itself in a full cycle accurate fashion Complete modeling of the deep partly protected pipeline with all the interrupt wait state and stall effects is performed The wrapper is thus reduced to a thin layer describing the interconnection to pins and the API between the ISA model and the BIM is simple Our solution provides full cycle and phase accuracy for the proposed implementation under real operating conditions for system on chip designs The accuracy is verified cycle by cycle against the gate RTL level model For the processor models the simulation slowdown that one might expect by the increased accuracy does not occur The SuperSim compiled ISA simulator of the processor 15 16 successfully compensates for slowdown due to increased accuracy In this paper we also describe the integration of these models with other hardware and software components A fully cycle accurate system simulation has been achieved incorporating the C based ISA DSP models and mixed level VHDL models The integration supports full multi processor debugging visibility and controllability of instantiable configurable models of the DSP processor with low development effort Experimental results demonstrate processor ISA model speeds of up to 123K cycles second and co verification model speeds of up to 70K cycles second For a complete RTL VHDL based system on chip simulation speedups of a factor of 10 over conventional RTL simulations were attained The paper is organized as follows Section 2 presents our DSP processor co verification model An integration of these models into a VHDL simulation environment is presented in Section 3 Experimental results are discussed in Section 4 and finally conclusions are presented in Section 5 2 PROCESSOR CO VERIFICATION MODEL This section presents the design options


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