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Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification



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Cycle and Phase Accurate DSP Modeling and Integration for HW SW Co Verification Lisa Guerra Joachim Fitzner Dipankar Talukdar Chris Schl ger Bassam Tabbara Vojin Zivojnovic Conexant Systems 4311 Jamboree Rd MC 510E 602 Newport Beach CA 92660 USA lisa guerra dipankar talukdar conexant com AXYS GmbH UC Berkeley EECS Dept Kaiserstr 100 211 150 Cory Hall 52134 Herzogenrath Germany Berkeley CA 94720 USA jf cs vz axys de tbassam eecs berkeley edu ABSTRACT We present our practical experience in the modeling and integration of cycle phase accurate instruction set architecture ISA models of digital signal processors DSPs with other hardware and software components A common approach to the modeling of processors for HW SW co verification relies on instruction accurate ISA models combined i e wrapped with the bus interface models BIM that generate the clock phase accurate timing at the component s interface pins However for DSPs and new microprocessors with complex architectural features this approach is from our perspective not acceptable The additional extensive modeling of the pipeline and other architectural details in the BIM would force us to develop two detailed processor models with a complex BIM API between them We therefore propose an alternative approach in which the processor ISAs themselves are modeled in a full cycle phase accurate fashion The bus interface model is then reduced to just modeling the connection to the pins Our models have been integrated into a number of cycle based and event driven system simulation environments We present one such experience in incorporating these models into a VHDL environment The accuracy has been verified cycle by cycle against the gate RTL level models Multiprocessor debugging and observability into the precise cycleaccurate processor state is provided The use of co verification models in place of the RTL resulted in system speedups up to 10 times with the cycle accurate ISA models themselves reaching performances of up to



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