Main PageDAC99Front MatterTable of ContentsSession IndexAuthor IndexCycle and Phase Accurate DSP Modeling and Integrationfor HW/SW Co-VerificationLisa Guerra*, Joachim Fitzner⊥, Dipankar Talukdar*, Chris Schläger⊥, Bassam Tabbara+,Vojin Zivojnovic⊥*Conexant Systems4311 Jamboree Rd., MC 510E-602,Newport Beach, CA 92660, USA[lisa.guerra,dipankar.talukdar]@conexant.com⊥ AXYS GmbH,Kaiserstr. 10052134 Herzogenrath, Germany[jf, cs, vz]@axys.de+UC Berkeley EECS Dept.211-150 Cory HallBerkeley, CA 94720, [email protected] present our practical experience in the modeling andintegration of cycle/phase-accurate instruction set architecture(ISA) models of digital signal processors (DSPs) with otherhardware and software components. A common approach to themodeling of processors for HW/SW co-verification relies oninstruction-accurate ISA models combined (i.e. wrapped) with thebus interface models (BIM) that generate the clock/phase-accuratetiming at the component’s interface pins. However, for DSPs andnew microprocessors with complex architectural features thisapproach is from our perspective not acceptable. The additionalextensive modeling of the pipeline and other architectural detailsin the BIM would force us to develop two detailed processormodels with a complex BIM API between them. We thereforepropose an alternative approach in which the processor ISAsthemselves are modeled in a full cycle/phase-accurate fashion.The bus interface model is then reduced to just modeling theconnection to the pins. Our models have been integrated into anumber of cycle-based and event-driven system simulationenvironments. We present one such experience in incorporatingthese models into a VHDL environment. The accuracy has beenverified cycle-by-cycle against the gate/RTL level models. Multi-processor debugging and observability into the precise cycle-accurate processor state is provided. The use of co-verificationmodels in place of the RTL resulted in system speedups up to 10times, with the cycle-accurate ISA models themselves reachingperformances of up to 123K cycles/sec.1. INTRODUCTIONThe trend of developing increasingly complex systems undershrinking time-to-market conditions continues. Typical current-day, single-chip electronic system implementations include a mixof a number of microcontroller, DSP, shared memory, dedicatedlogic, and interconnect components. With increased hardware andsoftware design complexity, greater use of components fromvarious design teams and third parties, and rising number of gatesper pin, verification has emerged as a critical bottlenecksurrounding the system-on-chip design paradigm.In addressing this verification bottleneck, concurrent simulation offull systems-on-chip with interacting hardware and software isnow widely recognized as an important and viable verificationapproach. Co-simulation/verification of hardware and softwarehas been proposed for a number of environments such as [8][3][12][5][10][13][4][15][2] and is also offered commercially bycompanies such as Mentor Graphics [9], Synopsys [14] andothers.In this work our interest is system co-simulation used duringcycle-accurate system verification, after the system architecturehas been selected and hardware and software models have beendeveloped. Co-simulation enables the verification of actualprocessor application code running on ISA processor models inconjunction with accurate models of the remainder of thehardware system.In general, for cycle-accurate processor modeling, there have beenefforts which develop C/C++-based cycle-accurate ISA models toverify against the RTL models (e.g., for the UltraSparc [11] andCRISP 32-bit RISC microprocessors [6]). On the other hand, inthe co-verification domain, the most common approach forcycle/phase-accurate modeling uses instruction-based ISA modelsextended by simple interface models (commonly referred to as businterface models (BIM) or wrappers) which interpret externalinteraction events, and thereby generate cycle/phase-accuratesimulation traces at the component’s pins. This method is used,for example, in the ARM7 processor model [7] integrated intocommercial HDL-based environments such as [14] and [9].For architectures with a simple timing, this can provide asatisfactory level of accuracy under most circumstances. RecentDSP architectures and a growing number of new microcontrollers,however, have deep pipelines with greater memory accessbandwidth, memory accesses distributed over multiple stages, andcomplex stalling logic. For these types of processors, bus interfacemodels become very complex, and must include modeling ofpipeline and architecture information in order to recover thenecessary timing. Our contribution described here offers analternative to detailed interface models; we model the processorISA itself in a full cycle-accurate fashion. Complete modeling ofthe deep, partly-protected pipeline with all the interrupt, waitstate, and stall effects is performed. The wrapper is thus reducedto a thin layer describing the interconnection to pins and the APIbetween the ISA model and the BIM is simple.Our solution provides full cycle and phase-accuracy for theproposed implementation under real operating conditions forsystem-on-chip designs. The accuracy is verified cycle-by-cycleagainst the gate/RTL-level model. For the processor models, thesimulation slowdown that one might expect by the increasedaccuracy does not occur. The SuperSim compiled ISA simulatorof the processor [15][16] successfully compensates for slowdowndue to increased accuracy.In this paper we also describe the integration of these models withother hardware and software components. A fully cycle-accuratesystem simulation has been achieved, incorporating the C-basedISA DSP models and mixed-level VHDL models. The integrationsupports full multi-processor debugging, visibility, andcontrollability of instantiable, configurable models of the DSPprocessor with low development effort. Experimental resultsdemonstrate processor ISA model speeds of up to 123Kcycles/second and co-verification model speeds of up to 70Kcycles/second. For a complete RTL