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EE 308 Spring 2010 Address Data and Control Buses A microprocessor system uses address data and control buses to communicate with external memory and memory mapped peripherals The address bus determines which memory location to access The control bus specifies whether the memory cycle is a read into microprocessor or a write out of microprocessor cycle and specifies timing information for the cycle The data bus contains the data being transfered during the memory cycle For example consider the following simple MC9S12 program which continuously increments the contents of address 0x0400 loop org 0x2000 inc bra 0x0400 loop The program is stored in memory starting at memory location 0x2000 The MC9S12 Program Counter starts at address 0x2000 The MC9S12 reads the first instruction inc 0x0400 located in address 0x2000 through 0x2002 The MC9S12 then reads the contents of memory location 0x0400 takes an internal memory cycle to increment the value then writes the new value out to address 0x0400 The MC9S12 then reads the next instruction bra 0x2000 The MC9S12 takes one memory cycle to load the program counter with the new value of 0x2000 and to clear its internal pipeline then reads the instruction at 0x2000 to figure out what to do next 1 EE 308 The MC9S12 address data and control buses simplified Note The following diagram assumes that the MC9S12 accesses one byte at a time The MC9S12 actually accesses two bytes 16 bits at a time when it can What actually occurs on the MC9S12 bus is a little more complicated than what is shown below MC9S12 ADDRESS DATA AND CONTROL BUS SIMPLIFIED ADDR 2000 2 DATA 72 2001 2002 0400 FFFF 04 00 A3 00 org 0x2000 inc 0x0400 bra loop 0400 2003 2004 FFFF 2000 20 FB 00 72 A4 R W loop 2000 2001 2002 2003 2004 72 04 00 20 FB inc 0x0400 bra 0x2000 Spring 2010 EE 308 Spring 2010 The MC9S12 Memory Map The MC9S12 has address regions occupied by internal memory and peripherals A diagram showing which address regions are used is called a memory map Here is a memory map of the MC9S12DP256 with no added memory or peripherals 0x0000 0x03FF 0x0400 0x0FFF 0x1000 0x3BFF 0x3C00 0x3FFF 0x4000 0x7FFF 0x8000 0xBFFF Registers 1 KB EEPROM 3 KB User RAM 11 KB D Bug 12 RAM 1 KB Flash EEPROM 16 KB Banked Flash EEPROM 16 KB 0xC000 0xFFFF D Bug 12 Flash EEPROM 3 16 KB EE 308 Spring 2010 The Expanded MC9S12 Memory Map We will add external peripherals to the MC9S12 First we will disable the Flash EEPROM at address 0x4000 through 0x7FFF which we are not using anyway Here is a memory map of the MC9S12DP256 with the peripherals we will add The peripherals will be put at 0x4000 and 0x4001 0x0000 Registers 1 KB EEPROM 3 KB User RAM 11 KB D Bug 12 RAM 1 KB 0x03FF 0x0400 0x0FFF 0x1000 0x3BFF 0x3C00 0x3FFF 0x4000 0x7FFF 0x8000 0xBFFF Unused Space Use address 0x4000 0x4001 for external peripherals Banked Flash EEPROM 16 KB 0xC000 0xFFFF D Bug 12 Flash EEPROM 16 KB 4 EE 308 Spring 2010 Simplified MC9S12 Write Cycle When the MC9S12 writes data to memory it does the following It puts the address it wants to write to on the address bus when E clock goes low It puts the data it wants to write onto the data bus It brings the Read Write R W line low to indicate a write The MC9S12 expects the external device at the given address will latch the data into its registers data on the falling edge of the E clock ADDR 16 DATA 16 MC9S12 MEMORY R W E LSTRB WRITE MC9S12 puts address on address bus puts data on data bus brings R W low Memory latches data on falling edge of E clock Example Write 0xfedc to address 0x3456 3457 E R W ADDR DATA 0x3456 0xfedc 5 EE 308 Spring 2010 Simplified MC9S12 Read Cycle When the MC9S12 reads data from memory it does the following It puts the address it wants to read from on the address bus when E clock goes low It brings the Read Write R W line high to indicate a read The MC9S12 expects the external device at the given address will put data on the data bus On the falling edge of the E clock the MC9S12 latches the data into its internal register ADDR 16 DATA 16 MC9S12 MEMORY R W E LSTRB READ MC9S12 puts address on address bus brings R W high Memory puts data on data bus HC12 latches data on falling edge of E clock Example Read from address 0x5678 0x5679 E R W ADDR DATA 0x5678 0xba98 6 EE 308 Spring 2010 The Real MC9S12DP256 Bus Up to now we have been using the MC9S12 in Single Chip Mode In Single Chip Mode the MC9S12 does not have an external address data bus The MC9S12 can be run in Expanded Mode In Expanded Mode the MC9S12 does have an external address data bus Things are a little more complicated on the real MC9S12DP256 bus than shown in the simplified diagrams above The MC9S12DP256 has a multiplexed address data bus The MC9S12DP256 sometimes accesses a single byte on a memory cycle and it sometimes access two bytes on a memory cycle The Multiplexed Address Data Bus The MC9S12DP256 has a limited number of pins it can use To have full 16 bit address bus and a full 16 bit data bus the MC9S12DP256 would need to use 32 extra pins in addition to several pins used for the control bus To save pin count Motorola uses the same set of pins for several purposes When put into expanded mode the MC9S12 uses the pins normally used for Ports A and B for its mulitplexed address and data bus When running in expanded mode you can no longer use Ports A and B as general purpose I O lines The MC9S12 uses the same sixteen line of Ports A and B for both address and data When the E clock is low the sixteen lines AD15 0 are used for address When the E clock is high the sixteen lines AD15 0 are used for data 7 EE 308 Spring 2010 The Multiplexed Address Data Bus ADDR 16 DATA 16 MC9S12 MEMORY R W E LSTRB MC9S12 has 16 bit address and 16 bit data buses Requires 35 bits Not enough pins on MC9S12 to allocate 35 pins for buses and pins for all other functions 8 EE 308 Spring 2010 Memory Chip Interface Memory chips need separate address and data bus Need way to de multiplex address and data lines from MC9S12 Memory chips need different control lines than the MC9S12 supplies These control lines are Chip Select goes low when the MC9S12 is accessing memory chip Write Enable goes low when the MC9S12 is writing to memory Output Enable goes low when the MC9S12 is reading from memory High Byte Enable goes low when the MC9S12 is accessing the High Byte Odd Address of memory Low Byte Enable goes low when the MC9S12 is accessing the Low Byte …


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