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Effectiveness and Limitations of Embedded Counter Based Performance Analysis



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CARNEGIE Department of Electrical MELLON and Computer Engineering Effectiveness and Limitations of Embedded Counter Based Performance Analysis Carey K Kloss 1997 Effectiveness and Limitations of Embedded Counter Based Performance Analysis Carey Ko Kloss 1997 Advisor Prof Shen Effectiveness and Limitations of Embedded Counter Based Performance Analysis Carey Kloss John Paul Shen Abstract This paper presents an experimentalstudy on the performanceof the Intel PentiumPro microprocessor using embedded performancecounters Thecounters enable detailed run time analysis of branchingand memory subsystemperformance and are accessed through a customdesignedtool The study uses Windows NTand realistic benchmarksincluding BAPco sSysmark32suite the Ziff Davis Winstone97PCBenchmarks and selected Spec95integer benchmarks The results showthat the PentiumPro memory subsystemand branchprediction are performingwell but the UOPper cycle and IPC numbersare low ThePentiumPro counters are not able to record enough informationabout the core of the CPUto analyze the reasons behindthe low UPC but wemakea conjecturethat the data hazardspresent betweeninstructions andUOPsare the causefor the poor performance Awishlist of countereventsthat wouldenablea morecompleteanalysis is provided 1 0 Introduction As microprocessors continue to develop from application specific machines to enormous general purpose systems comprehensive performance analysis is becoming increasingly Post silicon performance analysis is crucial more important to the design of future generation microprocessors Existing silicon allows the architect to run vast numbersof instructions through real systems providing true run time execution of application software However post silicon analysis has always been limited by the lack of visibility into the architecture provided by the pins In the past architects used logic analyzers to gather traces of pin behavior between the microprocessor and memoryor between modules in multiple chip



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