View Full Document

Progressive Register Allocation for Irregular Architectures



View the full content.
View Full Document
View Full Document

7 views

Unformatted text preview:

Progressive Register Allocation for Irregular Architectures David Koes dkoes cs cmu edu Seth Copen Goldstein seth cs cmu edu March 23 2005 2005 International Symposium on Code Generation and Optimization Irregular Architectures Few registers Register usage restrictions address registers hardwired registers Memory operands Examples x86 68k ColdFire ARM Thumb MIPS16 V800 various DSPs 2 2005 International Symposium on Code Generation and Optimization eax ebx ecx edx esi edi esp ebp Fewer Registers More Spills Percent of functions that spill 50 45 40 35 30 25 20 Percent 15 10 5 0 PPC 32 3 68k 16 x86 8 2005 International Symposium on Code Generation and Optimization Used gcc to compile 10 000 functions from Mediabench Spec95 Spec2000 and microbenchmarks Recorded which functions spilled Register Usage Restrictions Instructions may prefer or require a specific subset of registers x86 multiply instruction imul edx eax 2 byte instruction imul edx ecx 3 byte instruction x86 divide instruction idivl ecx eax edx eax ecx 4 2005 International Symposium on Code Generation and Optimization Memory Operands Load store not always needed to access variables allocated to memory depends upon instruction still less efficient than register access addl 8 ebp eax vs movl 8 ebp edx addl edx eax 5 2005 International Symposium on Code Generation and Optimization Register Allocation Challenges Optimize spill code with few registers spilling unavoidable Model register usage restrictions Exploit memory operands affects spilling decisions 6 2005 International Symposium on Code Generation and Optimization Previous Work Method Models Irregular Features Fast Optimal Graph Coloring Integer Programming Goodwin and Wilken 96 Kong and Wilken 98 Fu and Wilken 2002 Separated IP Appel and George 01 PBQP Scholz and Eckstein 02 7 2005 International Symposium on Code Generation and Optimization Our Goals Expressive Explicitly represent architectural irregularities and costs Proper model An optimum solution



Access the best Study Guides, Lecture Notes and Practice Exams

Loading Unlocking...
Login

Join to view Progressive Register Allocation for Irregular Architectures and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Progressive Register Allocation for Irregular Architectures and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?