Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71Slide 72Slide 73Slide 74Slide 75Slide 76Slide 77Slide 78Slide 79Slide 80Slide 81Slide 82Slide 83Slide 84Slide 85Slide 86Slide 87Slide 88Slide 89Slide 90Slide 91Slide 92Slide 93Slide 94Slide 95Slide 96Slide 97Slide 98Slide 99Slide 100Slide 101Slide 102Slide 103Slide 104Slide 105Slide 106Slide 107Slide 108Slide 109Slide 110Slide 111Slide 112Slide 113Slide 114Slide 115Slide 116Slide 117Slide 118Slide 119Slide 120Slide 121Slide 122Slide 123Slide 124Slide 125Slide 126Slide 127Slide 128Slide 129Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in the range of 0.02 to 0.1 m.Chapter 5 – Field-Effect Transistors (FETs)Field-Effect Transistors (FETs)Field-Effect Transistors (FETs)FET basic operational theory FET basic operational theory•The current controlled mechanism (drain current) is based on electric field established by the voltage applied to the control terminal (gate).•Current is only conducted by only one type of carrier “ electrons or holes” (that is why sometimes FET is called unipolar transistors. Another type is the insulated gate FET or IGFET.•Why MOS (Metal-Oxide) Transistors?•Very small (smaller silicone area on the IC)•Simple to manufacture•No need for biasing resistors.•Used in VLSI (very-large-scale integration)•The enhancement type MOSFET is the most significant semiconductor devise available today.Field-Effect Transistor (FET) Metal-oxide semiconductor field-effect transistor (MOSFET) has been extremely popular since the late 1970s.Compared to BJTs, MOS transistors:•Can be made smaller /higher integration scale•Easier to fabricate /lower manufacturing cost•Simpler circuitry for digital logic and memory•Inferior analog circuit performance (lower gain) Most digital ICs use MOS technologyRecent trend: more and more analog circuits are implemented in MOS technology for lower cost integration with digital circuits in a same chip•Four Terminals: Gate, Drain, Source, Body•Unlike the BJT, the MOSFET is normally constructed as a symmetrical device.•The name of Metal-Oxide-Semiconductor is apparent from the structure.•Typically, L = 0.15 to 10 µm, W = 0.3 to 500µm, the thickness of the oxide layer is in the range of 0.02 to 0.1 µ m.•The minimum value of L achievable in a particular MOS technology is often referred as the feature size of the technology.•State-of-the-art: Intel Pentium 4uses 0.13 µm technology•Modern technology uses poly-silicon which has high conductivity, instead of metal to form the gate.Field-Effect Transistors (FETs)Device StructurePhysical Operationof Enhancement MOSFETOperation with No Gate VoltageWith no bias applied to the gate, two back-to-back diodes exist in series between drain and source. The two back-to-back diodes prevent current conduction from drain to source when a voltage vDS is applied. The resistance is of the order of 10^12 ohmsCreating a Channel for Current FlowIf S and D are grounded and a positive voltage is applied to G, the holes are repelled from the channel region downwards, leaving behind a carrier-depletion region.Further increasing VG attracts minority carrier ( electrons) from the substrate into the channel region. When sufficient amount of electrons accumulate near the surface of the substrate under the gate, an n region is created-called as the inversion layer.When a small potential is applied across the Gate and source, it pushes away the holes towards the substrate and attract electrons from the Drain and Source into the channel region. When sufficient electrons are formulated beneath the Gate area, current flows between the Drain and the Source. (Basically the holes are pushed away in N channel – NMOS type to be replaced by the electrons from both the Source and the Drain creating a channel of N majority causing current to flow from Drain to Source.Physical Operation of Enhancement MOSFETApplying a Small vDSApplying a Small vDSApplying a small vDS (~ 0.1 or 0.2 V) causes a current iD to flow through the induced nchannel from D to S.The magnitude of iD depends on the density of electrons in the channel, which in turn depends on vGS.For vGS = Vt (threshold voltage), the channel is just induced and the conducted current is still negligibly small.As vGS > Vt, depth of the channel increases, iD will be proportional to (vGS – Vt), known as excess gate voltage or effective voltage.Increasing vGS above Vt enhances the channel, hence it is called enhancement type MOSFET.Note that iG=0.Physical Operation of Enhancement MOSFETOperation as vDS is IncreasedvDS appears as a voltage drop across the channel.Voltage across the oxide decreases from vGS at S to vGS-Vt at D.The channel depth will be tapered, and become more tapered as vDS is increased.Eventually, when vGS-vDS = Vt, the channel will be pinched off. Increasing vDS beyond this value has no effect on the channel shape and iD saturates (remains constant) at this value. The MOSFET enters the saturation region of operation.vDSsat = Vgs- VtvDSsatvGSVtvDSsatvGSVtvDSsatvGSVtvDSsatvGSVtPhysical Operation of Enhancement MOSFETThe drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.vDSsatvGSVtvDSsatvGSVtvDSsatvGSVtvDSsatvGSVtPhysical Operation of Enhancement MOSFETThe enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.Field-Effect Transistors (FETs) - Enhancement TypeAn NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the depletion region is not shown (for